527 lines
20 KiB
ReStructuredText
527 lines
20 KiB
ReStructuredText
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.. _architecture:
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HDL Architecture
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===============================================================================
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Every HDL design of a reference project can be divided into two
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subsystems:
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- **Base design** --- description of what the **carrier** contains:
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- an embedded processor - soft or hard
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- all the peripheral IPs (that are necessary to run a Linux
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distribution on the system)
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- these designs are specific to each carrier, making them **carrier
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dependent**
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- it describes part of the ``system_wrapper`` module
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- located in
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:git-hdl:`projects/common <master:projects/common>`;
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one for each carrier
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- **Board design** --- description of what the **board** attached to
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the carrier contains:
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- all the necessary IPs needed to support the board
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- these designs are common to all carriers, making them **carrier
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independent**
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- it describes part of the ``system_wrapper`` module
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- located in ``hdl/projects/$project_name/common/*bd.tcl``
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How they're instantiated
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-------------------------------------------------------------------------------
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In case of a project, inside the ``system_bd.tcl`` file, we have to source
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the *base design first*, then the *board design*.
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Example
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Take `AD-FMCOMMS2-EBZ`_ with ZedBoard; the ``system_bd.tcl`` will look like the
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following:
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.. code-block:: bash
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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source ../common/fmcomms2_bd.tcl
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Typical project diagram
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-------------------------------------------------------------------------------
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|HDL overall system|
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Base Design
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-------------------------------------------------------------------------------
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The base design contains all the I/O peripherals, memory interfaces
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and processing components, which are necessary for a fully functional
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Linux system. The majority of these components are Intel and AMD Xilinx IP
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cores.
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Usually, they contain:
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- Microprocessor
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- Memory interface controller
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- Peripheral interfaces
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Microprocessor
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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In our designs, we use only two types:
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.. list-table::
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:widths: 20 20 20 20 20
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:header-rows: 2
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* - Intel
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-
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- AMD Xilinx
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-
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-
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* - **SoC**
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- **FPGA**
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- **SoC**
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- **FPGA**
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- `ACAP`_
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* - `HPS`_
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- `NIOS II`_
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- `PS7`_
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`PS8`_
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- `MicroBlaze`_
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- `Versal`_
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.. _ACAP: https://www.xilinx.com/an/adaptive-compute-acceleration-platforms.html
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.. _HPS: https://www.intel.com/content/www/us/en/docs/programmable/683458/current/hard-processor-system-hps.html
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.. _NIOS II: https://www.intel.com/content/www/us/en/products/programmable/processor/nios-ii.html
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.. _PS7: https://www.xilinx.com/products/intellectual-property/processing_system7.html
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.. _PS8: https://www.xilinx.com/products/intellectual-property/zynq-ultra-ps-e.html
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.. _MicroBlaze: https://www.xilinx.com/products/design-tools/microblaze.html
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.. _Versal: https://www.xilinx.com/products/silicon-devices/acap/versal.html
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Worth mentioning in case of SoCs, the **Hard Processor System** (HPS)
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or **Processing System 7/8** (PS7/8) do not contain just the dual-core
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ARM® Cortex® - A9 MPCore™ processor, they also have other integrated
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peripherals and memory interfaces. For more information please visit
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the manufacturer's website, listed in the table above.
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- ``PS7`` --- `Zynq-7000 SoC Processing
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System <https://docs.xilinx.com/v/u/en-US/pg082-processing-system7>`__
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(``processing_system7``)
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- ``PS8`` --- `Zynq UltraScale+ MPSoC Processing
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System <https://docs.xilinx.com/viewer/book-attachment/xFC3qkokxbD~75kj6nPLuw/2o4flzqn5OqWHaMHwpG3Qg>`__
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(``zynq_ultra_ps_e``)
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- ``Versal`` --- `Versal ACAP
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CIPS <https://docs.xilinx.com/r/en-US/pg352-cips/Overview>`__
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(``versal_cips``)
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Memory Interface Controller
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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In almost all cases, the carrier board is not made and designed by
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Analog Devices, so the external memory solution of the system is given.
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Meaning we can not support, modify or alter this important part of the
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system, in several cases we even have system limitations because of it
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(e.g. the memory interface is not fast enough to handle the required
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data throughput).
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Under the two links below the user can find the landing page of the
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available memory solutions for both Intel and AMD:
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- Intel's memory interfaces:
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https://www.intel.com/content/www/us/en/programmable/support/support-resources/external-memory.html
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- AMD's memory interfaces:
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https://www.xilinx.com/products/intellectual-property/mig.html#documentation
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Peripheral interfaces
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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These interfaces are used to control external peripherals located on
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the prototyping board or the FMC IO board.
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In HDL, these ports are named slightly different than how they're in
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the documentations. Thus, to make it easier for beginners, here you
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have the naming of the ports depending on the microprocessor used.
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CPU/Memory interconnects addresses
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The memory addresses that will be used by software are based on the HDL
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addresses of the IP register map, to which an offset is added, depending
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on the architecture of the used FPGA (see also :git-hdl:`ad_cpu_interconnect
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procedure <master:projects/scripts/adi_board.tcl>`; architecture is
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specified by ``sys_zynq`` variable, for AMD FPGAs).
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**Zynq-7000 and 7 Series**
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Because this was the original target, this is the reference
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address used, the common one, to which depending on the architecture,
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you add an offset to get to the address space for the peripherals (as they
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differ from one to the other).
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**Zynq UltraScale+ MP**
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If the address is between 0x4000_0000 - 0x4FFF_FFFF then the
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AXI peripherics will be placed in 0x8000_0000 - 0x8FFF_FFFF range
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by adding 0x4000_0000 to the address.
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If the address is between 0x7000_0000 - 0x7FFF_FFFF then the
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AXI peripherics will be placed in 0x9000_0000 - 0x9FFF_FFFF range
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by adding 0x2000_0000 to the address.
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**Versal**
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If the address is between 0x4400_0000 - 0x4FFF_FFFF then the
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AXI peripherics will be placed in 0xA400_0000 - 0xAFFF_FFFF range
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by adding 0x6000_0000 to the address.
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If the address is between 0x7000_0000 - 0x7FFF_FFFF then the
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AXI peripherics will be placed in 0xB000_0000 - 0xBFFF_FFFF range
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by adding 0x4000_0000 to the address.
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SPI
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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In general, the base system has two Serial Peripheral Interfaces, which
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are used as a control interface for FMC/HSMC devices. These SPI
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interfaces are controlled by the integrated SPI controller of the **Hard
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Processor System** (HPS) or **Processing System 7/8** (PS7/8) or an
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Intel or AMD SPI controller core.
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I2C/I2S/SPDIF
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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A couple of carrier boards require these standard interfaces for
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different purposes, for example, a configuration interface for an audio
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peripheral device. These peripherals do not necessarily have vital roles
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in the reference design, it's more like a generic goal to support all
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the provided peripherals of the carrier board.
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HDMI
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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There is HDMI support for all the carriers which are using the ADV7511
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as HDMI transmitter. The HDMI transmitter core can be found
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`here <https://github.com/analogdevicesinc/hdl/tree/master/library/axi_hdmi_tx>`__.
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GPIOs
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The general rule of thumb is to define 64 GPIO pins for the base design:
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- bits [31: 0] always belong to the carrier board;
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- bits [63:32] will be assigned to switches, buttons and/or LEDs, which
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can be found on the FMC board.
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- bits [95:64] will be used when the FPGA type is Zynq UltraScale+
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MPSoC
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When some of these GPIOs are not used, the input pins should have the
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output pins driven to them, so that Vivado will not complain about
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inputs not being assigned to.
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Depending on the processor type, add these values to the GPIO number
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from the HDL project to obtain the final number used in software:
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- PS7 EMIO offset = 54
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- PS8 EMIO offset = 78
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Connectivity
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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- Ethernet
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- USB OTG
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These interfaces designs are borrowed from the golden reference design
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of the board.
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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When developing the Linux software parts for an HDL project, the
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interrupts number to the PS have a different number in the software
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side.
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Not a rule, but in our designs we preffer to use firstly the interrupts
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from 15 and to go down to 0. Be careful when assigning one, because it
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might be used in the base design of the carrier!
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Always check which are used (in
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``/projects/common/$carrier/$carrier_system_bd.tcl``)
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Interrupts table
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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=== ========== =========== ============ ============= ====== =============== ================
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HDL Linux Zynq Actual Zynq Linux ZynqMP Actual ZynqMP S10SoC Linux Cyclone V Actual Cyclone V
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=== ========== =========== ============ ============= ====== =============== ================
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15 59 91 111 143 32 55 87
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14 58 90 110 142 31 54 86
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13 57 89 109 141 30 53 85
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12 56 88 108 140 29 52 84
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11 55 87 107 139 28 51 83
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10 54 86 106 138 27 50 82
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9 53 85 105 137 26 49 81
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8 52 84 104 136 25 48 80
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7 36 68 96 128 24 47 79
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6 35 67 95 127 23 46 78
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5 34 66 94 126 22 45 77
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4 33 65 93 125 21 44 76
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3 32 64 92 124 20 43 75
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2 31 63 91 123 19 42 74
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1 30 62 90 122 18 41 73
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0 29 61 89 121 17 40 72
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=== ========== =========== ============ ============= ====== =============== ================
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Board design and capabilities
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-------------------------------------------------------------------------------
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AMD platforms
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 16 16 18 18 16 16
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:header-rows: 1
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* - Board name
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- Boots from
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- FMC connector 1
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- FMC connector 2
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- VADJ FMC connector
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- Family
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* - `AC701 <https://www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.html>`__
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- JTAG
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- HPC (2 GTP @ 6.6 Gbps)
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- ---
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- 3.3V/**\*2.5V**/1.8V
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- Artix-7
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* - `Cora Z7-07S <https://digilent.com/reference/programmable-logic/cora-z7/start>`__
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- SD card
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- ---
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- ---
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- ---
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- Zynq-7000
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* - `KC705 <https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html>`__
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- JTAG
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- HPC (4 GTX @ 10.3125 Gbps)
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- LPC (1 GTX @ 10.3125 Gbps)
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- 3.3V/**\*2.5V**/1.8V
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- Kintex-7
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* - `KCU105 <https://www.xilinx.com/products/boards-and-kits/kcu105.html>`__
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- JTAG
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- HPC (8 GTH @ 16.3 Gbps)
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- LPC (1 GTH @ 16.3 Gbps)
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- **\*1.8V**/1.5V/1.2V
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- Kintex UltraScale
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* - `Microzed <http://zedboard.org/product/microzed>`__
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- JTAG
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- ---
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- ---
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- ---
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- Zynq-7000
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* - `VC707 <https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html>`__
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- JTAG
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- HPC (8 GTX @ 12.5 Gbps)
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- HPC (8 GTX @ 12.5 Gbps)
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- **\*1.8V**/1.5V/1.2V
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- Virtex-7
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* - `VC709 <https://www.xilinx.com/products/boards-and-kits/dk-v7-vc709-g.html>`__
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- JTAG
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- HPC (10 GTH @ 13.1 Gbps)
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- ---
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- **\*1.8V**
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- Virtex-7
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* - `VCK190 <https://www.xilinx.com/products/boards-and-kits/vck190.html>`__
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- SD card
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- FMC+ (12 GTY @ 28.21 Gbps)
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- FMC+ (12 GTY @ 28.21 Gbps)
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- **\*1.5V**/1.2V
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- Versal AI Core
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* - `VCU118 <https://www.xilinx.com/products/boards-and-kits/vcu118.html>`__
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- JTAG
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- FMC+ (24 GTY @ 28.21 Gbps)
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- LPC
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- **\*1.8V**/1.5V/1.2V
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- Virtex UltraScale+
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* - `VCU128 <https://www.xilinx.com/products/boards-and-kits/vcu128.html>`__
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- JTAG
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- FMC+ (24 GTY @ 28.21 Gbps)
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- ---
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- **\*1.8V**/1.5V/1.2V
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- Virtex UltraScale+ HBM
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* - `VMK180 <https://www.xilinx.com/products/boards-and-kits/vmk180.html>`__
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- SD card
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- FMC+ (12 GTY @ 28.21 Gbps)
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- FMC+ (12 GTY @ 28.21 Gbps)
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- **\*1.5V**/1.2V
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- Versal Prime Series
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* - `ZC702 <https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html>`__
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- SD card
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- LPC
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- LPC
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- 3.3V/**\*2.5V**/1.8V
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- Zynq-7000
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* - `ZC706 <https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html>`__
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- SD card
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- HPC (8 GTX @ 10.3125 Gbps)
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- LPC (1 GTX @ 10.3125 Gbps)
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- 3.3V/**\*2.5V**/1.8V
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- Zynq-7000
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* - `ZCU102 <https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-es2-g.html>`__
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- SD card
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- HPC (8 GTH @ 16.3 Gbps)
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- HPC (8 GTH @ 16.3 Gbps)
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- **\*1.8V**/1.5V/1.2V
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- Zynq UltraScale+ MP SoC
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* - `ZedBoard <https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/>`__
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- SD card
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- LPC
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- ---
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- 3.3V/2.5V/**\*1.8V**
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- Zynq-7000
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.. note::
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|||
|
The column with the VADJ value applies to the FMC connectors when they
|
|||
|
exist. If both of them exist, then it is the same for both of them.
|
|||
|
If there is only one FMC connector, then it applies to only one.
|
|||
|
If both are missing, then a --- (dash) will appear.
|
|||
|
|
|||
|
.. note::
|
|||
|
|
|||
|
**(\* bold**) = default VADJ
|
|||
|
FMC1 & FMC2 columns -> depending on the power supply of the device
|
|||
|
connected to the FMC, the custom VADJ will have the value supported by
|
|||
|
both the carrier and the device(s)
|
|||
|
|
|||
|
Intel platforms
|
|||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|||
|
|
|||
|
.. list-table::
|
|||
|
:widths: 20 40 40
|
|||
|
:header-rows: 1
|
|||
|
|
|||
|
* - Board name
|
|||
|
- FMC connector 1
|
|||
|
- FMC connector 2
|
|||
|
* - `A10GX <https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html>`__
|
|||
|
- LPC ()
|
|||
|
- HPC (8 x 17.4 Gbps)
|
|||
|
* - `A10SoC <https://www.altera.com/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html>`__
|
|||
|
- HPC (8)
|
|||
|
- LPC (8)
|
|||
|
* - `S10SoC <https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-sx.html>`__
|
|||
|
- FMC+ (24 @ 28.3 Gbps)
|
|||
|
- FMC+ (24 @ 28.3 Gbps)
|
|||
|
|
|||
|
VADJ values
|
|||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|||
|
|
|||
|
.. list-table::
|
|||
|
:widths: 20 40 40
|
|||
|
:header-rows: 1
|
|||
|
|
|||
|
* - Board name
|
|||
|
- FMC connector 1
|
|||
|
- FMC connector 2
|
|||
|
* - `A10GX <https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html>`__
|
|||
|
- **\*1.8V**/1.5V/1.35V/1.2V
|
|||
|
- **\*1.8V**/1.5V/1.35V/1.2V
|
|||
|
* - `A10SoC <https://www.altera.com/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html>`__
|
|||
|
- **\*1.8V**/1.5V/1.35V/1.25V/1.2V/1.1V
|
|||
|
- **\*1.8V**/1.5V/1.35V/1.2V/1.1V
|
|||
|
* - `S10SoC <https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-sx.html>`__
|
|||
|
- **\*3.3V**/1.8V/1.2V
|
|||
|
- **\*3.3V**/1.8V/1.2V
|
|||
|
|
|||
|
(**\* bold**) = default VADJ
|
|||
|
FMC1 & FMC2 columns -> depending on the power supply of the device
|
|||
|
connected to the FMC, the custom VADJ will have the value supported by
|
|||
|
both the carrier and the device(s)
|
|||
|
|
|||
|
|
|||
|
File structure of a project
|
|||
|
-------------------------------------------------------------------------------
|
|||
|
|
|||
|
.. tip::
|
|||
|
|
|||
|
In ``/projects/common/$carrier_name/`` you can find templates for the
|
|||
|
*system_top.v*, *Makefile*, etc. to help you when creating a new project.
|
|||
|
|
|||
|
Project files for AMD boards
|
|||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|||
|
|
|||
|
A project for an AMD FPGA board should contain the following files:
|
|||
|
|
|||
|
- ``Makefile`` --- auto-generated file; contains all the IP
|
|||
|
dependencies needed for the project to be built
|
|||
|
|
|||
|
- ``system_project.tcl`` --- script that creates the actual Vivado
|
|||
|
project and runs the synthesis/implementation of the design
|
|||
|
|
|||
|
- ``system_bd.tcl`` --- sources the *base design first*, then the
|
|||
|
*board design*, and afterwards it contains all the IP instances and
|
|||
|
connections that must be added on top of the sourced files, to
|
|||
|
complete the design of the project (these are specific to the
|
|||
|
combination of this carrier and board)
|
|||
|
|
|||
|
- ``system_constr.xdc`` --- constraints file of the design; it’s the
|
|||
|
connection between the physical pins of the FPGA that you want to use
|
|||
|
and the HDL code that describes the behavior; here you define the FMC
|
|||
|
I/O pins, board-specific clock signals, timing constraints, etc. The
|
|||
|
constraints specific to the carrier are imported in the
|
|||
|
*system_project.tcl* file
|
|||
|
|
|||
|
- ``system_top.v`` --- contains everything about the HDL part of the
|
|||
|
project; it instantiates the ``system_wrapper`` module, IO buffers,
|
|||
|
I/ODDRs, modules that transform signals from LVDS to single-ended,
|
|||
|
etc. The I/O ports of this Verilog module will be connected to actual
|
|||
|
I/O pads of the FPGA.
|
|||
|
|
|||
|
- ``system_wrapper`` --- is a tool generated file and can be found at
|
|||
|
``<project_name>.srcs/sources_1/bd/system/hdl/system_wrapper.v``
|
|||
|
|
|||
|
- the I/O ports of this module are declared in either
|
|||
|
*system_bd.tcl* or in the **board** design file
|
|||
|
- this can be visualized in Vivado at the Block Design section
|
|||
|
- the base design, board design and system_bd.tcl describe this
|
|||
|
module, making the connections between the instantiated IPs
|
|||
|
|
|||
|
Project files for Intel boards
|
|||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|||
|
|
|||
|
A project for an Intel FPGA board should contain the following files:
|
|||
|
|
|||
|
- ``Makefile`` --- auto-generated file; contains all the IP
|
|||
|
dependencies needed for the project to be built
|
|||
|
|
|||
|
- ``system_project.tcl`` --- script that creates the actual Quartus
|
|||
|
project and runs the synthesis/implementation of the design. It also
|
|||
|
contains the I/O definitions for the interfaces between the board and
|
|||
|
the FPGA
|
|||
|
|
|||
|
- ``system_qsys.tcl`` --- also called **platform designer**; sources
|
|||
|
the *base design first*, then the *board design*, and afterwards it
|
|||
|
contains all the IP instances and connections that must be added on
|
|||
|
top of the sourced files, to complete the design of the project
|
|||
|
(these are specific to the combination of this carrier and board)
|
|||
|
|
|||
|
- ``system_constr.sdc`` --- contains clock definitions and other path
|
|||
|
constraints
|
|||
|
|
|||
|
- ``system_top.v`` --- contains everything about the HDL part of the
|
|||
|
project; it instantiates the ``system_wrapper`` module, IO buffers,
|
|||
|
I/ODDRs, modules that transform signals from LVDS to single-ended,
|
|||
|
etc. The I/O ports of this Verilog module will be connected to actual
|
|||
|
I/O pads of the FPGA
|
|||
|
|
|||
|
Examples
|
|||
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|||
|
|
|||
|
Some carriers have a different name for these files, for example A10SoC
|
|||
|
has constraints file for both PL side and PS side:
|
|||
|
|
|||
|
- a10soc_plddr4_assign.tcl --- constraints file for the PL
|
|||
|
- a10soc_system_assign.tcl --- constraints file for the PS
|
|||
|
|
|||
|
.. _AD-FMCOMMS2-EBZ: https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD-FMCOMMS2.html
|
|||
|
|
|||
|
.. |HDL overall system| image:: ./sources/base_platform.svg
|