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pluto_hdl_adi/library/axi_ad4858/axi_ad4858_constr.ttcl

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axi_ad4858: Initial commit The axi_ad4858 IP core is design as the HDL interface for the AD4858 ADC. Features: - AXI based configuration - LVDS and CMOS support - Configurable number of active data lines (CMOS - build-time configurable) - Oversampling support - Supports packet formats 0,1,2 or 3 - CRC check support - Real-time data header access - Channel based raw data access(0x0408) - Xilinx devices compatible Documentation at https://wiki.analog.com/resources/fpga/docs/axi_ad4858
2023-02-13 17:42:15 +00:00
###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName [ttcl_add $ComponentName "_constr"] :>
<: setFileExtension ".xdc" :>
<: setFileProcessingOrder late :>
<: set lvds_cmos_n [getBooleanValue "LVDS_CMOS_N"] :>
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
<: if {$lvds_cmos_n} { :>
set_false_path -quiet \
-from $up_clk \
-to [get_cells -quiet -hier -filter {name =~ *packet_format_reg* && IS_SEQUENTIAL}]
set_false_path -quiet \
-from $up_clk \
-to [get_cells -quiet -hier -filter {name =~ *ch_*_base_reg* && IS_SEQUENTIAL}]
set_false_path -quiet \
-from [get_cells -hier -filter {name =~ *packet_format_reg* && IS_SEQUENTIAL}] \
-to [get_cells -quiet -hieri -filter {name =~ *packet_cnt_length_reg* && IS_SEQUENTIAL}]
<: } :>