pluto_hdl_adi/library/util_cic/cic_int.v

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// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
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// The user should read each of these license terms, and understand the
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module cic_int #(
  parameter DATA_WIDTH = 12,
  parameter STAGE_WIDTH = 1,
  parameter NUM_STAGES = 1
) (
  input clk,
  input [NUM_STAGES-1:0] ce,
  input [DATA_WIDTH-1:0] data_in,
  output [DATA_WIDTH-1:0] data_out
);

  reg [DATA_WIDTH-1:0] state = 'h00;
  wire [DATA_WIDTH-1:0] sum;
  wire [DATA_WIDTH-1:0] mask;

  assign data_out = state;
  assign sum = (data_in & mask) + (state & mask);
  generate
  genvar i;

  for (i = 0; i < NUM_STAGES; i = i + 1) begin
    localparam j = NUM_STAGES - i - 1;
    localparam H = DATA_WIDTH - STAGE_WIDTH * i - 1;
    localparam L = j == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (i+1);

    assign mask[H:L] = {{H-L{1'b1}},j != 0 ? ce[j] : 1'b1};

    always @(posedge clk) begin
      if (ce[j] == 1'b1) begin
        state[H:L] <= sum[H:L];
      end
    end
  end

  endgenerate

endmodule