2023-07-06 12:08:22 +00:00
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###############################################################################
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## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2022-08-10 08:29:05 +00:00
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# ad777x
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add_instance axi_ad777x_adc axi_ad777x
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add_interface axi_ad777x_adc_if conduit end
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set_interface_property axi_ad777x_adc_if EXPORT_OF axi_ad777x_adc.adc_if
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add_interface axi_ad777x_adc_clk_if conduit end
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set_interface_property axi_ad777x_adc_clk_if EXPORT_OF axi_ad777x_adc.if_clk_in
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# adc-path channel pack
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add_instance ad777x_adc_pack util_cpack2
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set_instance_parameter_value ad777x_adc_pack {NUM_OF_CHANNELS} {8}
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set_instance_parameter_value ad777x_adc_pack {SAMPLE_DATA_WIDTH} {32}
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add_connection axi_ad777x_adc.if_adc_clk ad777x_adc_pack.clk
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add_connection axi_ad777x_adc.if_adc_reset ad777x_adc_pack.reset
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add_connection axi_ad777x_adc.if_adc_dovf ad777x_adc_pack.if_fifo_wr_overflow
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add_connection ad777x_adc_pack.adc_ch_0 axi_ad777x_adc.adc_ch_0
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add_connection ad777x_adc_pack.adc_ch_1 axi_ad777x_adc.adc_ch_1
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add_connection ad777x_adc_pack.adc_ch_2 axi_ad777x_adc.adc_ch_2
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add_connection ad777x_adc_pack.adc_ch_3 axi_ad777x_adc.adc_ch_3
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add_connection ad777x_adc_pack.adc_ch_4 axi_ad777x_adc.adc_ch_4
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add_connection ad777x_adc_pack.adc_ch_5 axi_ad777x_adc.adc_ch_5
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add_connection ad777x_adc_pack.adc_ch_6 axi_ad777x_adc.adc_ch_6
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add_connection ad777x_adc_pack.adc_ch_7 axi_ad777x_adc.adc_ch_7
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# adc(ad777x-dma)
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add_instance ad777x_dma axi_dmac
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set_instance_parameter_value ad777x_dma {ID} {0}
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set_instance_parameter_value ad777x_dma {DMA_DATA_WIDTH_SRC} {256}
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set_instance_parameter_value ad777x_dma {DMA_DATA_WIDTH_DEST} {64}
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set_instance_parameter_value ad777x_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value ad777x_dma {AXI_SLICE_DEST} {0}
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set_instance_parameter_value ad777x_dma {AXI_SLICE_SRC} {0}
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set_instance_parameter_value ad777x_dma {SYNC_TRANSFER_START} {1}
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set_instance_parameter_value ad777x_dma {CYCLIC} {0}
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set_instance_parameter_value ad777x_dma {DMA_TYPE_DEST} {0}
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set_instance_parameter_value ad777x_dma {DMA_TYPE_SRC} {2}
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add_connection sys_clk.clk ad777x_dma.s_axi_clock
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add_connection sys_clk.clk ad777x_dma.m_dest_axi_clock
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add_connection sys_clk.clk axi_ad777x_adc.s_axi_clock
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add_connection axi_ad777x_adc.if_adc_clk ad777x_dma.if_fifo_wr_clk
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add_connection ad777x_adc_pack.if_packed_fifo_wr_en ad777x_dma.if_fifo_wr_en
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add_connection ad777x_adc_pack.if_packed_fifo_wr_sync ad777x_dma.if_fifo_wr_sync
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add_connection ad777x_adc_pack.if_packed_fifo_wr_data ad777x_dma.if_fifo_wr_din
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add_connection ad777x_adc_pack.if_packed_fifo_wr_overflow ad777x_dma.if_fifo_wr_overflow
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#resets
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add_connection sys_dma_clk.clk_reset axi_ad777x_adc.s_axi_reset
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add_connection sys_clk.clk_reset ad777x_dma.s_axi_reset
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add_connection sys_dma_clk.clk_reset ad777x_dma.m_dest_axi_reset
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# interrupts
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ad_cpu_interrupt 5 ad777x_dma.interrupt_sender
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# cpu interconnects
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ad_cpu_interconnect 0x00020000 axi_ad777x_adc.s_axi
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ad_cpu_interconnect 0x00030000 ad777x_dma.s_axi
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# mem interconnects
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ad_dma_interconnect ad777x_dma.m_dest_axi
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