2023-04-06 06:24:19 +00:00
|
|
|
// ***************************************************************************
|
|
|
|
// ***************************************************************************
|
2023-07-06 13:54:40 +00:00
|
|
|
// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
|
2023-04-06 06:24:19 +00:00
|
|
|
//
|
|
|
|
// In this HDL repository, there are many different and unique modules, consisting
|
|
|
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
|
|
|
// developed independently, and may be accompanied by separate and unique license
|
|
|
|
// terms.
|
|
|
|
//
|
|
|
|
// The user should read each of these license terms, and understand the
|
|
|
|
// freedoms and responsibilities that he or she has by using this source/core.
|
|
|
|
//
|
|
|
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
|
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
|
|
|
// A PARTICULAR PURPOSE.
|
|
|
|
//
|
|
|
|
// Redistribution and use of source or resulting binaries, with or without modification
|
|
|
|
// of this file, are permitted under one of the following two license terms:
|
|
|
|
//
|
|
|
|
// 1. The GNU General Public License version 2 as published by the
|
|
|
|
// Free Software Foundation, which can be found in the top level directory
|
|
|
|
// of this repository (LICENSE_GPL2), and also online at:
|
|
|
|
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
|
|
|
//
|
|
|
|
// OR
|
|
|
|
//
|
|
|
|
// 2. An ADI specific BSD license, which can be found in the top level directory
|
|
|
|
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
|
|
|
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
|
|
|
// This will allow to generate bit files and not release the source code,
|
|
|
|
// as long as it attaches to an ADI device.
|
|
|
|
//
|
|
|
|
// ***************************************************************************
|
|
|
|
// ***************************************************************************
|
|
|
|
|
|
|
|
`timescale 1ns/100ps
|
|
|
|
|
|
|
|
module system_top (
|
|
|
|
|
|
|
|
output fan_en_b
|
|
|
|
);
|
|
|
|
|
|
|
|
wire [94:0] gpio_i;
|
|
|
|
wire [94:0] gpio_o;
|
|
|
|
|
|
|
|
assign gpio_i[94:1] = gpio_o[94:1];
|
|
|
|
|
|
|
|
assign fan_en_b = gpio_o[0];
|
|
|
|
|
|
|
|
// instantiations
|
|
|
|
system_wrapper i_system_wrapper (
|
|
|
|
.gpio_i (gpio_i),
|
|
|
|
.gpio_o (gpio_o),
|
|
|
|
.gpio_t (),
|
|
|
|
|
|
|
|
.spi0_csn (),
|
|
|
|
.spi0_miso (1'b0),
|
|
|
|
.spi0_mosi (),
|
|
|
|
.spi0_sclk ());
|
|
|
|
|
|
|
|
endmodule
|