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pluto_hdl_adi/projects/imageon/common/imageon_bd.tcl

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imageon: Initial commit Initial commit of the IMAGEON project for ZC706. NOT tested.
2015-01-08 15:01:22 +00:00
imageon: updates
2015-03-24 19:08:22 +00:00
# adv7511 (reconfigure base design)
imageon: Initial commit Initial commit of the IMAGEON project for ZC706. NOT tested.
2015-01-08 15:01:22 +00:00
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_out_clk]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_vsync]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_hsync]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_data_e]]]
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports hdmi_data]]]
imageon: updates
2015-03-24 19:08:22 +00:00
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
delete_bd_objs [get_bd_ports hdmi_out_clk]
delete_bd_objs [get_bd_ports hdmi_vsync]
delete_bd_objs [get_bd_ports hdmi_hsync]
delete_bd_objs [get_bd_ports hdmi_data_e]
delete_bd_objs [get_bd_ports hdmi_data]
imageon: Initial commit Initial commit of the IMAGEON project for ZC706. NOT tested.
2015-01-08 15:01:22 +00:00
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
set_property CONFIG.EMBEDDED_SYNC {1} [get_bd_cells axi_hdmi_core]
imageon: Invert HDMI TX clock The ADV7511 samples the parallel data bus at the rising edge of sample clock. Generate the clock so that the falling edge is aligned to updating the bus data. This creates larger timing margins on each side of the sampling edge and makes the design more robust. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:43:04 +00:00
set_property CONFIG.OUT_CLK_POLARITY {1} [get_bd_cells axi_hdmi_core]
imageon_zc706: Update the project to the new framework
2015-03-23 10:45:34 +00:00
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
create_bd_port -dir O hdmi_tx_clk
create_bd_port -dir O -from 15 -to 0 hdmi_tx_data
imageon_zc706: Update the project to the new framework
2015-03-23 10:45:34 +00:00
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
ad_connect hdmi_tx_clk axi_hdmi_core/hdmi_out_clk
ad_connect hdmi_tx_data axi_hdmi_core/hdmi_16_es_data
imageon: updates
2015-03-24 19:08:22 +00:00
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
# adv7611
imageon: updates
2015-03-24 19:08:22 +00:00
set axi_hdmi_rx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_rx:1.0 axi_hdmi_rx_core]
set axi_hdmi_rx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_hdmi_rx_dma]
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_hdmi_rx_dma
axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 07:13:39 +00:00
set_property -dict [list CONFIG.DMA_2D_TRANSFER {1}] $axi_hdmi_rx_dma
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {14}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_hdmi_rx_dma
imageon: Increase RX DMA FIFO size Increase the RX DMA FIFO to be able to better compensate for momentarily memory bus contention. This has shown to resolve occasional overflows that would occur under high system memory load. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 13:10:59 +00:00
set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_hdmi_rx_dma
imageon: updates
2015-03-24 19:08:22 +00:00
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
create_bd_port -dir I hdmi_rx_clk
create_bd_port -dir I -from 15 -to 0 hdmi_rx_data
imageon: updates
2015-03-24 19:08:22 +00:00
ad_connect hdmi_rx_clk axi_hdmi_rx_core/hdmi_rx_clk
ad_connect hdmi_rx_data axi_hdmi_rx_core/hdmi_rx_data
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
imageon: Connect hdmi_rx_core output clock to DMA Connect the HDMI RX core output clock to the DMA rather than connecting the HDMI RX input clock directly. This will allow the HDMI RX core to modify the clock and e.g. insert clock buffers or similar. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 12:15:15 +00:00
ad_connect axi_hdmi_rx_core/hdmi_clk axi_hdmi_rx_dma/fifo_wr_clk
imageon: updates
2015-03-24 19:08:22 +00:00
ad_connect axi_hdmi_rx_core/hdmi_dma_sof axi_hdmi_rx_dma/fifo_wr_sync
ad_connect axi_hdmi_rx_core/hdmi_dma_de axi_hdmi_rx_dma/fifo_wr_en
ad_connect axi_hdmi_rx_core/hdmi_dma_data axi_hdmi_rx_dma/fifo_wr_din
ad_connect axi_hdmi_rx_core/hdmi_dma_ovf axi_hdmi_rx_dma/fifo_wr_overflow
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
ad_connect axi_hdmi_rx_core/hdmi_dma_unf GND
ad_connect sys_cpu_resetn axi_hdmi_rx_dma/m_dest_axi_aresetn
ad_cpu_interconnect 0x43100000 axi_hdmi_rx_core
ad_cpu_interconnect 0x43C20000 axi_hdmi_rx_dma
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_hdmi_rx_dma/m_dest_axi
ad_cpu_interrupt ps-12 mb-12 axi_hdmi_rx_dma/irq
# spdif tx
delete_bd_objs [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_ports spdif]]]
delete_bd_objs [get_bd_ports spdif]
create_bd_port -dir O spdif_tx
ad_connect spdif_tx axi_spdif_tx_core/spdif_tx_o
# spdif rx
create_bd_port -dir I spdif_rx
imageon: updates
2015-03-24 19:08:22 +00:00
imageon_ZC706: Add axi_spdif_rx core to the design
2015-07-03 14:48:29 +00:00
set axi_spdif_rx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_rx:1.0 axi_spdif_rx_core]
imageon/common: Fix parameter name for spdif_rx
2015-09-29 15:50:41 +00:00
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_rx_core
set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_rx_core
imageon_ZC706: Add axi_spdif_rx core to the design
2015-07-03 14:48:29 +00:00
imageon: moved spdif_rx to DMA3 to be compatible with both zc706 and zed
2015-07-09 07:58:54 +00:00
set_property -dict [list CONFIG.PCW_USE_DMA3 {1}] $sys_ps7
imageon_ZC706: Add axi_spdif_rx core to the design
2015-07-03 14:48:29 +00:00
ad_connect sys_cpu_clk axi_spdif_rx_core/DMA_REQ_ACLK
imageon: moved spdif_rx to DMA3 to be compatible with both zc706 and zed
2015-07-09 07:58:54 +00:00
ad_connect sys_cpu_clk sys_ps7/DMA3_ACLK
imageon_ZC706: Add axi_spdif_rx core to the design
2015-07-03 14:48:29 +00:00
ad_connect sys_cpu_resetn axi_spdif_rx_core/DMA_REQ_RSTN
imageon: moved spdif_rx to DMA3 to be compatible with both zc706 and zed
2015-07-09 07:58:54 +00:00
ad_connect sys_ps7/DMA3_REQ axi_spdif_rx_core/DMA_REQ
ad_connect sys_ps7/DMA3_ACK axi_spdif_rx_core/DMA_ACK
imageon_ZC706: Add axi_spdif_rx core to the design
2015-07-03 14:48:29 +00:00
ad_connect spdif_rx axi_spdif_rx_core/spdif_rx_i
ad_cpu_interconnect 0x75C20000 axi_spdif_rx_core
imageon: updates
2015-03-24 19:08:22 +00:00
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
# iic interface
imageon_zc706: Update project + Connect the Rx path to HP2 + Enable AXI_SLICE_DEST + Add ILA to the dma_fifo and dma_axi_s2mm interface + Fix constraints
2015-04-01 15:50:18 +00:00
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
set axi_iic_imageon [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_imageon]
set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_imageon
set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_imageon
imageon_zc706: Update project + Connect the Rx path to HP2 + Enable AXI_SLICE_DEST + Add ILA to the dma_fifo and dma_axi_s2mm interface + Fix constraints
2015-04-01 15:50:18 +00:00
imageon/zc706- board updates
2016-06-01 17:54:45 +00:00
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_imageon
ad_connect iic_imageon axi_iic_imageon/iic
ad_cpu_interconnect 0x43C40000 axi_iic_imageon
ad_cpu_interrupt ps-11 mb-11 axi_iic_imageon/iic2intc_irpt
Revert "imageon: Connect raw data to ILA" This reverts commit 9e4fb2d048eb69cfdc1c5970abce856216a6be20. This conflicts with moving the capture FF into the IOB. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 13:38:22 +00:00