zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/projects/dac_fmc_ebz/a10soc/Makefile

21 lines
749 B
Makefile
Raw Normal View History

dac_fmc_ebz: Add initial Arria10 SoC support Add support for the Arria 10 SoC development kit to the dac_fmc_ebz project. This allows to use the following FMC boards on the Arria 10 SoC development Kit carrier: * AD9135-FMC-EBZ * AD9136-FMC-EBZ * AD9144-FMC-EBZ * AD9152-FMC-EBZ * AD9154-FMC-EBZ * AD9171-FMC-EBZ * AD9172-FMC-EBZ * AD9173-FMC-EBZ Note that the board in its default configuration is not fully compatible with the mentioned FMC boards and some slight re-work moving some 0 Ohm resistors is required. The rework concerns the LA01 and LA05 pins, which by default are not connected to the FPGA. The changes required are: LA01_P_CC R612: R0 -> DNI R610: DNI -> R0 LA01_N_CC R613: R0 -> DNI R611: DNI -> R0 LA05_P R621: R0 -> DNI R620: DNI -> R0 LA05_N R633: R0 -> DNI R632: DNI -> R0 The main differences between AD9144-FMC-EBZ and AD9172-FMC-EBZ are: * The DAC txen signals are connected to different pins * The polarity of the spi_en signal is active low instead of active high * The maximum lane rate is up to 15.4 Gpbs To accommodate this all 4 possible txen signals as well as the spi_en signal are connected to GPIOs. Software can decide how to use them depending on which FMC board is connected. Note that each carrier has a maximum supported lane rate. Modes of the AD9172 (and similar) that exceed the carrier specific limit can not be used on that carrier. The limits are as following: * A10SoC: 14.2 Gbps
2018-03-20 13:43:36 +00:00
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := dac_fmc_ebz_a10soc
M_DEPS += ../common/dac_fmc_ebz_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
M_DEPS += ../../common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_plddr4_assign.tcl
LIB_DEPS += altera/adi_jesd204
LIB_DEPS += altera/avl_dacfifo
LIB_DEPS += axi_dmac
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
LIB_DEPS += util_pack/util_upack2
include ../../scripts/project-altera.mk