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pluto_hdl_adi/library/xilinx/util_adxcvr/util_adxcvr_constr.xdc

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Add copyright and license to .xdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-10 08:38:46 +00:00
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
util_adxcvr- rstdone on usrclk2
2016-07-13 19:23:02 +00:00
Update Vivado version to 2020.2 Update vivado version to 2020.2: - update default vivado version from 2020.1 to 2020.2 - add conditions to apply specific contraints only in Out Of Context mode. - update DDR controler parameters for vcu118 and kcu105 dev boards
2021-06-03 11:39:31 +00:00
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *rx_rate*}]
set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *tx_rate*}]
util_adxcvr- rstdone on usrclk2
2016-07-13 19:23:02 +00:00
set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
util_adxcvr- add constraints file
2016-07-15 14:19:48 +00:00
set_false_path -to [get_cells -hier -filter {name =~ *rx_rate_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *tx_rate_m1_reg* && IS_SEQUENTIAL}]
util_adxcvr- rstdone on usrclk2
2016-07-13 19:23:02 +00:00
xilinx:adxcvr: PRBS support The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal PRBS generators and checkers allowing the testing the multi-gigabit serial link at the physical layer without the need of the link layer bringup.
2020-12-18 14:43:28 +00:00
# sync bits i_sync_bits_tx_prbs_in
set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_bits_tx_prbs_in* && IS_SEQUENTIAL}
]
# sync bits i_sync_bits_rx_prbs_in
set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_bits_rx_prbs_in* && IS_SEQUENTIAL}
]
# sync bits i_sync_bits_rx_prbs_out
set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
adxcvr: Increase version to 17.5.a Add suport for XCVR phase adjust buffer status: - Expose TXBUFSTATUS and RXBUFSTATUS - Create RXBUFSTATUS_RST flag for clearing RXBUFSTATUS
2021-10-01 14:41:30 +00:00
-filter {NAME =~ *i_sync_bits_rx_prbs_out* && IS_SEQUENTIAL}
]
# sync bits i_sync_bits_rx_bufstatus_in
set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_bits_rx_bufstatus_in* && IS_SEQUENTIAL}
]
# sync bits i_sync_bits_bufstatus_out
set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_bits_bufstatus_out* && IS_SEQUENTIAL}]