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pluto_hdl_adi/projects/ad9213_dual_ebz/s10soc/system_qsys.tcl

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Add copyright and license to .tcl, .ttcl files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-06 12:08:22 +00:00
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
ad9213_dual_ebz: Initial commit Used ADF4377 SPI configuration CPOL/CPHA 1 for increasing the reliability of the level translators ad9213_dual_ebz/s10soc: Redesign the address layout avl_peripheral_mm_bridge 0x0000000 0x0001FFFF * sys_gpio_in 0x00000000 * sys_gpio_out 0x00000020 * sys_spi 0x00000040 * sys_gpio_bd 0x000000D0 * sys_id 0x000000E0 avl_mm_bridge_0 0x00040000 0x0007FFFF * ad9213_rx_0.phy_reconfig_0 0x00000000 * ad9213_rx_0.phy_reconfig_1 0x00002000 * ad9213_rx_0.phy_reconfig_2 0x00004000 * ad9213_rx_0.phy_reconfig_3 0x00006000 * ad9213_rx_0.phy_reconfig_4 0x00008000 * ad9213_rx_0.phy_reconfig_5 0x0000A000 * ad9213_rx_0.phy_reconfig_6 0x0000C000 * ad9213_rx_0.phy_reconfig_7 0x0000E000 * ad9213_rx_0.phy_reconfig_8 0x00010000 * ad9213_rx_0.phy_reconfig_9 0x00012000 * ad9213_rx_0.phy_reconfig_10 0x00014000 * ad9213_rx_0.phy_reconfig_11 0x00016000 * ad9213_rx_0.phy_reconfig_12 0x00018000 * ad9213_rx_0.phy_reconfig_13 0x0001A000 * ad9213_rx_0.phy_reconfig_14 0x0001C000 * ad9213_rx_0.phy_reconfig_15 0x0001E000 * ad9213_rx_0.link_pll_reconfig 0x00020000 avl_mm_bridge_1 0x00080000 0x000BFFFF * ad9213_rx_1.phy_reconfig_0 0x00000000 * ad9213_rx_1.phy_reconfig_1 0x00002000 * ad9213_rx_1.phy_reconfig_2 0x00004000 * ad9213_rx_1.phy_reconfig_3 0x00006000 * ad9213_rx_1.phy_reconfig_4 0x00008000 * ad9213_rx_1.phy_reconfig_5 0x0000A000 * ad9213_rx_1.phy_reconfig_6 0x0000C000 * ad9213_rx_1.phy_reconfig_7 0x0000E000 * ad9213_rx_1.phy_reconfig_8 0x00010000 * ad9213_rx_1.phy_reconfig_9 0x00012000 * ad9213_rx_1.phy_reconfig_10 0x00014000 * ad9213_rx_1.phy_reconfig_11 0x00016000 * ad9213_rx_1.phy_reconfig_12 0x00018000 * ad9213_rx_1.phy_reconfig_13 0x0001A000 * ad9213_rx_1.phy_reconfig_14 0x0001C000 * ad9213_rx_1.phy_reconfig_15 0x0001E000 * ad9213_rx_1.link_pll_reconfig 0x00020000 Connected directly to the h2s_lw_axi_master * ad9213_rx_0.link_reconfig 0x000C0000 * ad9213_rx_0.link_management 0x000C4000 * ad9213_rx_1.link_reconfig 0x000C8000 * ad9213_rx_1.link_management 0x000CC000 * axi_ad9213_0.s_axi 0x000D0000 * axi_ad9213_1.s_axi 0x000D1000 * axi_ad9213_dma_0.s_axi 0x000D2000 * axi_ad9213_dma_1.s_axi 0x000D3800
2019-09-09 14:06:06 +00:00
s10soc: Update base desgin from ES to production, H-Tile version
2021-07-02 12:10:09 +00:00
set adc_fifo_address_width 15
ad9213_dual_ebz: Initial commit Used ADF4377 SPI configuration CPOL/CPHA 1 for increasing the reliability of the level translators ad9213_dual_ebz/s10soc: Redesign the address layout avl_peripheral_mm_bridge 0x0000000 0x0001FFFF * sys_gpio_in 0x00000000 * sys_gpio_out 0x00000020 * sys_spi 0x00000040 * sys_gpio_bd 0x000000D0 * sys_id 0x000000E0 avl_mm_bridge_0 0x00040000 0x0007FFFF * ad9213_rx_0.phy_reconfig_0 0x00000000 * ad9213_rx_0.phy_reconfig_1 0x00002000 * ad9213_rx_0.phy_reconfig_2 0x00004000 * ad9213_rx_0.phy_reconfig_3 0x00006000 * ad9213_rx_0.phy_reconfig_4 0x00008000 * ad9213_rx_0.phy_reconfig_5 0x0000A000 * ad9213_rx_0.phy_reconfig_6 0x0000C000 * ad9213_rx_0.phy_reconfig_7 0x0000E000 * ad9213_rx_0.phy_reconfig_8 0x00010000 * ad9213_rx_0.phy_reconfig_9 0x00012000 * ad9213_rx_0.phy_reconfig_10 0x00014000 * ad9213_rx_0.phy_reconfig_11 0x00016000 * ad9213_rx_0.phy_reconfig_12 0x00018000 * ad9213_rx_0.phy_reconfig_13 0x0001A000 * ad9213_rx_0.phy_reconfig_14 0x0001C000 * ad9213_rx_0.phy_reconfig_15 0x0001E000 * ad9213_rx_0.link_pll_reconfig 0x00020000 avl_mm_bridge_1 0x00080000 0x000BFFFF * ad9213_rx_1.phy_reconfig_0 0x00000000 * ad9213_rx_1.phy_reconfig_1 0x00002000 * ad9213_rx_1.phy_reconfig_2 0x00004000 * ad9213_rx_1.phy_reconfig_3 0x00006000 * ad9213_rx_1.phy_reconfig_4 0x00008000 * ad9213_rx_1.phy_reconfig_5 0x0000A000 * ad9213_rx_1.phy_reconfig_6 0x0000C000 * ad9213_rx_1.phy_reconfig_7 0x0000E000 * ad9213_rx_1.phy_reconfig_8 0x00010000 * ad9213_rx_1.phy_reconfig_9 0x00012000 * ad9213_rx_1.phy_reconfig_10 0x00014000 * ad9213_rx_1.phy_reconfig_11 0x00016000 * ad9213_rx_1.phy_reconfig_12 0x00018000 * ad9213_rx_1.phy_reconfig_13 0x0001A000 * ad9213_rx_1.phy_reconfig_14 0x0001C000 * ad9213_rx_1.phy_reconfig_15 0x0001E000 * ad9213_rx_1.link_pll_reconfig 0x00020000 Connected directly to the h2s_lw_axi_master * ad9213_rx_0.link_reconfig 0x000C0000 * ad9213_rx_0.link_management 0x000C4000 * ad9213_rx_1.link_reconfig 0x000C8000 * ad9213_rx_1.link_management 0x000CC000 * axi_ad9213_0.s_axi 0x000D0000 * axi_ad9213_1.s_axi 0x000D1000 * axi_ad9213_dma_0.s_axi 0x000D2000 * axi_ad9213_dma_1.s_axi 0x000D3800
2019-09-09 14:06:06 +00:00
source $ad_hdl_dir/projects/common/s10soc/s10soc_system_qsys.tcl
source $ad_hdl_dir/projects/common/intel/adcfifo_qsys.tcl
Updated the makefiles to build the projects in subdirectories based on the build parameters. Running 'make' will build the default project directly in the project folder (like it did before) Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory. Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory. Running 'make clean' will clean the default project only. Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build. Running 'make clean-all' will delete all the built configurations and libraries. Note that the 'JESD' and 'LANE' words from the parameter names are stripped. Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-09-23 09:28:22 +00:00
if [info exists ad_project_dir] {
source ../../common/ad9213_dual_qsys.tcl
} else {
source ../common/ad9213_dual_qsys.tcl
}