2023-07-06 12:08:22 +00:00
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###############################################################################
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## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2019-03-21 06:24:45 +00:00
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
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# create a SPI Engine architecture
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create_bd_cell -type hier spi
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current_bd_instance /spi
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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ad_ip_instance spi_engine_execution execution
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2020-08-15 09:29:45 +00:00
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ad_ip_parameter execution CONFIG.DATA_WIDTH 16
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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2019-03-21 06:24:45 +00:00
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ad_ip_instance axi_spi_engine axi
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2020-08-15 09:29:45 +00:00
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ad_ip_parameter axi CONFIG.DATA_WIDTH 16
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ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
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2019-03-21 06:24:45 +00:00
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2020-08-15 09:29:45 +00:00
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ad_ip_instance spi_engine_offload offload
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2019-03-21 06:24:45 +00:00
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ad_ip_parameter offload CONFIG.DATA_WIDTH 16
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2020-08-15 09:29:45 +00:00
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ad_ip_instance spi_engine_interconnect interconnect
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2019-03-21 06:24:45 +00:00
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH 16
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2020-08-15 09:29:45 +00:00
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2019-03-21 06:24:45 +00:00
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## to setup the sample rate of the system change the PULSE_PERIOD value
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2020-08-15 09:29:45 +00:00
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## the actual sample rate will be PULSE_PERIOD * (1/sys_cpu_clk)
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2019-03-21 06:24:45 +00:00
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set cycle_per_sec_100mhz 100000000
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set sampling_cycle [expr int(ceil(double($cycle_per_sec_100mhz) / $adc_sampling_rate))]
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2020-08-15 09:29:45 +00:00
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ad_ip_instance axi_pulse_gen trigger_gen
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ad_ip_parameter trigger_gen CONFIG.ASYNC_CLK_EN 0
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2019-03-21 06:24:45 +00:00
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ad_ip_parameter trigger_gen CONFIG.PULSE_PERIOD $sampling_cycle
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ad_ip_parameter trigger_gen CONFIG.PULSE_WIDTH 1
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2020-08-15 09:29:45 +00:00
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# clocks
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2019-03-21 06:24:45 +00:00
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ad_connect clk offload/spi_clk
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ad_connect clk offload/ctrl_clk
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ad_connect clk execution/clk
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ad_connect clk axi/s_axi_aclk
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ad_connect clk axi/spi_clk
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ad_connect clk interconnect/clk
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2020-08-15 09:29:45 +00:00
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ad_connect clk trigger_gen/s_axi_aclk
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2019-03-21 06:24:45 +00:00
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2020-08-15 09:29:45 +00:00
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# resets
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ad_connect resetn axi/s_axi_aresetn
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ad_connect resetn trigger_gen/s_axi_aresetn
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2019-03-21 06:24:45 +00:00
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ad_connect axi/spi_resetn offload/spi_resetn
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ad_connect axi/spi_resetn execution/resetn
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ad_connect axi/spi_resetn interconnect/resetn
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2020-08-15 09:29:45 +00:00
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# interfaces
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ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi M_AXIS_SAMPLE
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ad_connect execution/spi m_spi
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2019-03-21 06:24:45 +00:00
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ad_connect trigger_gen/pulse offload/trigger
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2020-08-15 09:29:45 +00:00
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2019-03-21 06:24:45 +00:00
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ad_connect irq axi/irq
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current_bd_instance /
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ad_ip_instance axi_dmac axi_adaq7980_dma
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ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adaq7980_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adaq7980_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_adaq7980_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_adaq7980_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_DATA_WIDTH_SRC 16
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ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect sys_cpu_clk spi/clk
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ad_connect sys_cpu_resetn spi/resetn
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ad_connect sys_cpu_resetn axi_adaq7980_dma/m_dest_axi_aresetn
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ad_connect spi/m_spi spi
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ad_connect axi_adaq7980_dma/s_axis spi/M_AXIS_SAMPLE
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ad_cpu_interconnect 0x44a00000 spi/axi
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2020-08-15 09:29:45 +00:00
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ad_cpu_interconnect 0x44a10000 spi/trigger_gen
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2019-03-21 06:24:45 +00:00
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ad_cpu_interconnect 0x44a30000 axi_adaq7980_dma
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ad_connect sys_cpu_clk axi_adaq7980_dma/s_axis_aclk
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ad_cpu_interrupt "ps-13" "mb-13" axi_adaq7980_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" spi/irq
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_adaq7980_dma/m_dest_axi
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