pluto_hdl_adi/library/xilinx/util_clkdiv/util_clkdiv_ip.tcl

source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

adi_ip_create util_clkdiv
adi_ip_files util_clkdiv [list \
  "util_clkdiv_constr.xdc" \
  "util_clkdiv_ooc.ttcl" \
  "util_clkdiv.v" ]

adi_ip_properties_lite util_clkdiv

adi_ip_ttcl util_clkdiv "util_clkdiv_ooc.ttcl"

set_property processing_order LATE [ipx::get_files "util_clkdiv_constr.xdc" \
                  -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]]

set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]

set_property value_validation_type list [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]
set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]

set_property value_validation_type list [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]

set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]

adi_add_bus clk_out master "xilinx.com:signal:clock_rtl:1.0" "xilinx.com:signal:clock:1.0" \
  [list {"clk_out" "CLK"}]

ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

ipx::save_core [ipx::current_core]
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips 2022-07-12 11:06:15 +00:00			`source ../../../scripts/adi_env.tcl`
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2018-08-14 09:59:39 +00:00			`source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl`
util_clkdiv: Added division by 2 option 2016-11-24 14:01:37 +00:00
util_clkdiv: Add IP 2016-09-30 14:13:51 +00:00			`adi_ip_create util_clkdiv`
			`adi_ip_files util_clkdiv [list \`
util_clkdiv: Add constraint file 2017-01-11 16:11:53 +00:00			`"util_clkdiv_constr.xdc" \`
util_clkdiv: set OOC default clock constraints 2019-04-12 14:29:52 +00:00			`"util_clkdiv_ooc.ttcl" \`
util_clkdiv: Add constraint file 2017-01-11 16:11:53 +00:00			`"util_clkdiv.v" ]`
util_clkdiv: Added division by 2 option 2016-11-24 14:01:37 +00:00
util_clkdiv: Add IP 2016-09-30 14:13:51 +00:00			`adi_ip_properties_lite util_clkdiv`
util_clkdiv: Added division by 2 option 2016-11-24 14:01:37 +00:00
util_clkdiv: set OOC default clock constraints 2019-04-12 14:29:52 +00:00			`adi_ip_ttcl util_clkdiv "util_clkdiv_ooc.ttcl"`

util_clkdiv: constraints should be applied LATE for this core 2017-04-03 15:14:29 +00:00			`set_property processing_order LATE [ipx::get_files "util_clkdiv_constr.xdc" \`
			`-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ synthesis}]]`

util_clkdiv: Added division by 2 option 2016-11-24 14:01:37 +00:00			`set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]`

util_clkdiv: Make the clock division parametrizable and changed C_SIM_DEVICE to SIM_DEVICE 2017-01-16 12:35:42 +00:00			`set_property value_validation_type list [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]`
			`set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]`

			`set_property value_validation_type list [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]`
util_clkdiv: Keep as valid only settings common for 7Series and Ultrascale 2017-01-18 09:56:24 +00:00			`set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]`
util_clkdiv: Make the clock division parametrizable and changed C_SIM_DEVICE to SIM_DEVICE 2017-01-16 12:35:42 +00:00
			`set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]`
util_clkdiv: Keep as valid only settings common for 7Series and Ultrascale 2017-01-18 09:56:24 +00:00			`set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]`
util_clkdiv: Added Ultrascale support and switch to BUFGMUX_CTRL for glitch free switching 2017-01-13 11:54:07 +00:00
util_clkdiv: Register output port as a clock (#33) If the output pin is not defined as a clock, some of the Vivado IPI propagation TCL will error out. Signed-off-by: Matt Fornero <matt.fornero@mathworks.com> 2017-06-19 06:40:53 +00:00			`adi_add_bus clk_out master "xilinx.com:signal:clock_rtl:1.0" "xilinx.com:signal:clock:1.0" \`
			`[list {"clk_out" "CLK"}]`

axi_*: Infer clock and reset signals of an IP A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip 2018-02-15 08:41:14 +00:00			`ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]`

util_clkdiv: Add IP 2016-09-30 14:13:51 +00:00			`ipx::save_core [ipx::current_core]`