pluto_hdl_adi/library/util_upack/util_upack.v

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_upack #(
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parameter CHANNEL_DATA_WIDTH = 32,
parameter NUM_OF_CHANNELS = 8) (
// dac interface
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input dac_clk,
input dac_enable_0,
input dac_valid_0,
output dac_valid_out_0,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_0,
input dac_enable_1,
input dac_valid_1,
output dac_valid_out_1,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_1,
input dac_enable_2,
input dac_valid_2,
output dac_valid_out_2,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_2,
input dac_enable_3,
input dac_valid_3,
output dac_valid_out_3,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_3,
input dac_enable_4,
input dac_valid_4,
output dac_valid_out_4,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_4,
input dac_enable_5,
input dac_valid_5,
output dac_valid_out_5,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_5,
input dac_enable_6,
input dac_valid_6,
output dac_valid_out_6,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_6,
input dac_enable_7,
input dac_valid_7,
output dac_valid_out_7,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_7,
// fifo interface
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output dac_valid,
output dac_sync,
input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] dac_data);
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// internal parameters
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localparam MAX_CHANNELS = 8;
// internal registers
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reg dac_valid_int = 'd0;
reg dac_sync_int = 'd0;
// internal signals
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wire dac_valid_s;
wire [ 7:0] dac_enable_s;
wire dac_dsf_valid_m_s;
wire [((CHANNEL_DATA_WIDTH*MAX_CHANNELS)-1):0] dac_dsf_data_m_s;
wire [ 7:0] dac_dmx_enable_m_s;
wire [(MAX_CHANNELS-1):0] dac_dsf_req_s;
wire [(MAX_CHANNELS-1):0] dac_dsf_sync_s;
wire [(MAX_CHANNELS-1):0] dac_dsf_valid_s;
wire [((CHANNEL_DATA_WIDTH*MAX_CHANNELS)-1):0] dac_dsf_data_s[(MAX_CHANNELS-1):0];
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_valid_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_7_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_6_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_5_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_4_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_3_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_2_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_1_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_0_s;
// data interleaving
assign dac_valid = dac_valid_int;
assign dac_sync = dac_sync_int;
assign dac_valid_out_0 = dac_dmx_valid_s[0];
assign dac_valid_out_1 = dac_dmx_valid_s[0];
assign dac_valid_out_2 = dac_dmx_valid_s[0];
assign dac_valid_out_3 = dac_dmx_valid_s[0];
assign dac_valid_out_4 = dac_dmx_valid_s[0];
assign dac_valid_out_5 = dac_dmx_valid_s[0];
assign dac_valid_out_6 = dac_dmx_valid_s[0];
assign dac_valid_out_7 = dac_dmx_valid_s[0];
always @(posedge dac_clk) begin
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dac_valid_int <= | dac_dsf_req_s;
dac_sync_int <= | dac_dsf_sync_s;
end
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assign dac_valid_s = dac_valid_7 | dac_valid_6 | dac_valid_5 | dac_valid_4 |
dac_valid_3 | dac_valid_2 | dac_valid_1 | dac_valid_0;
assign dac_enable_s = {dac_enable_7, dac_enable_6, dac_enable_5, dac_enable_4,
dac_enable_3, dac_enable_2, dac_enable_1, dac_enable_0};
assign dac_dsf_valid_m_s = | dac_dsf_valid_s;
assign dac_dsf_data_m_s = dac_dsf_data_s[7] | dac_dsf_data_s[6] |
dac_dsf_data_s[5] | dac_dsf_data_s[4] | dac_dsf_data_s[3] |
dac_dsf_data_s[2] | dac_dsf_data_s[1] | dac_dsf_data_s[0];
assign dac_dmx_enable_m_s[7] = | dac_dmx_enable_7_s;
assign dac_dmx_enable_m_s[6] = | dac_dmx_enable_6_s;
assign dac_dmx_enable_m_s[5] = | dac_dmx_enable_5_s;
assign dac_dmx_enable_m_s[4] = | dac_dmx_enable_4_s;
assign dac_dmx_enable_m_s[3] = | dac_dmx_enable_3_s;
assign dac_dmx_enable_m_s[2] = | dac_dmx_enable_2_s;
assign dac_dmx_enable_m_s[1] = | dac_dmx_enable_1_s;
assign dac_dmx_enable_m_s[0] = | dac_dmx_enable_0_s;
// instantiations
genvar n;
generate
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// defaults
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for (n = NUM_OF_CHANNELS; n < MAX_CHANNELS; n = n + 1) begin: g_defaults
assign dac_dsf_req_s[n] = 'd0;
assign dac_dsf_sync_s[n] = 'd0;
assign dac_dsf_valid_s[n] = 'd0;
assign dac_dsf_data_s[n] = 'd0;
end
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// dsf
for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_dsf
util_upack_dsf #(
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
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.CHANNEL_DATA_WIDTH (CHANNEL_DATA_WIDTH),
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.NUM_OF_CHANNELS (NUM_OF_CHANNELS),
.MAX_CHANNELS (MAX_CHANNELS),
.SEL_CHANNELS ((n+1)))
i_dsf (
.dac_clk (dac_clk),
.dac_valid (dac_valid_s),
.dac_data (dac_data),
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.dac_dmx_enable (dac_dmx_enable_m_s[n]),
.dac_dsf_req (dac_dsf_req_s[n]),
.dac_dsf_sync (dac_dsf_sync_s[n]),
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.dac_dsf_valid (dac_dsf_valid_s[n]),
.dac_dsf_data (dac_dsf_data_s[n]));
end
// demux
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for (n = 0; n < (CHANNEL_DATA_WIDTH/16); n = n + 1) begin: g_dmx
util_upack_dmx i_dmx (
.dac_clk (dac_clk),
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.dac_enable (dac_enable_s),
.dac_valid (dac_dmx_valid_s[n]),
.dac_data_0 (dac_data_0[((16*n)+15):(16*n)]),
.dac_data_1 (dac_data_1[((16*n)+15):(16*n)]),
.dac_data_2 (dac_data_2[((16*n)+15):(16*n)]),
.dac_data_3 (dac_data_3[((16*n)+15):(16*n)]),
.dac_data_4 (dac_data_4[((16*n)+15):(16*n)]),
.dac_data_5 (dac_data_5[((16*n)+15):(16*n)]),
.dac_data_6 (dac_data_6[((16*n)+15):(16*n)]),
.dac_data_7 (dac_data_7[((16*n)+15):(16*n)]),
.dac_dmx_enable ({dac_dmx_enable_7_s[n], dac_dmx_enable_6_s[n],
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dac_dmx_enable_5_s[n], dac_dmx_enable_4_s[n], dac_dmx_enable_3_s[n],
dac_dmx_enable_2_s[n], dac_dmx_enable_1_s[n], dac_dmx_enable_0_s[n]}),
.dac_dsf_valid (dac_dsf_valid_m_s),
.dac_dsf_data (dac_dsf_data_m_s[((MAX_CHANNELS*16*(n+1))-1):(MAX_CHANNELS*16*n)]));
end
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endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************