2015-11-04 11:31:50 +00:00
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package require -exact qsys 15.0
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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set_module_property NAME util_adcfifo
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set_module_property DESCRIPTION "ADC FIFO utility"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME util_adcfifo
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL util_adcfifo
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add_fileset_file ad_axis_inf_rx.v VERILOG PATH ../common/ad_axis_inf_rx.v
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add_fileset_file ad_mem_asym.v VERILOG PATH ../common/ad_mem_asym.v
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add_fileset_file util_adcfifo.v VERILOG PATH util_adcfifo.v TOP_LEVEL_FILE
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add_fileset_file util_adcfifo_constr.sdc SDC PATH util_adcfifo_constr.sdc
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# parameters
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add_parameter ADC_DATA_WIDTH INTEGER 0
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set_parameter_property ADC_DATA_WIDTH DEFAULT_VALUE 256
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set_parameter_property ADC_DATA_WIDTH DISPLAY_NAME ADC_DATA_WIDTH
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set_parameter_property ADC_DATA_WIDTH TYPE INTEGER
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set_parameter_property ADC_DATA_WIDTH UNITS None
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set_parameter_property ADC_DATA_WIDTH HDL_PARAMETER true
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add_parameter DMA_DATA_WIDTH INTEGER 0
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set_parameter_property DMA_DATA_WIDTH DEFAULT_VALUE 64
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set_parameter_property DMA_DATA_WIDTH DISPLAY_NAME DMA_DATA_WIDTH
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set_parameter_property DMA_DATA_WIDTH TYPE INTEGER
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set_parameter_property DMA_DATA_WIDTH UNITS None
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set_parameter_property DMA_DATA_WIDTH HDL_PARAMETER true
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add_parameter DMA_READY_ENABLE INTEGER 0
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set_parameter_property DMA_READY_ENABLE DEFAULT_VALUE 1
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set_parameter_property DMA_READY_ENABLE DISPLAY_NAME DMA_READY_ENABLE
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set_parameter_property DMA_READY_ENABLE TYPE INTEGER
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set_parameter_property DMA_READY_ENABLE UNITS None
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set_parameter_property DMA_READY_ENABLE HDL_PARAMETER true
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add_parameter DMA_ADDRESS_WIDTH INTEGER 0
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set_parameter_property DMA_ADDRESS_WIDTH DEFAULT_VALUE 10
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set_parameter_property DMA_ADDRESS_WIDTH DISPLAY_NAME DMA_ADDRESS_WIDTH
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set_parameter_property DMA_ADDRESS_WIDTH TYPE INTEGER
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set_parameter_property DMA_ADDRESS_WIDTH UNITS None
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set_parameter_property DMA_ADDRESS_WIDTH HDL_PARAMETER true
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# defaults
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ad_alt_intf clock adc_clk input 1 adc_clk
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ad_alt_intf reset adc_rst input 1 if_adc_clk
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2015-11-25 08:20:06 +00:00
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ad_alt_intf signal adc_wr input 1 valid
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ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data
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2015-11-04 11:31:50 +00:00
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ad_alt_intf signal adc_wovf output 1 adc_dovf
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ad_alt_intf clock dma_clk input 1 clk
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ad_alt_intf signal dma_wr output 1 valid
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ad_alt_intf signal dma_wdata output DMA_DATA_WIDTH data
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ad_alt_intf signal dma_wready input 1 ready
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ad_alt_intf signal dma_xfer_req input 1 xfer_req
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