pluto_hdl_adi/library/axi_adrv9001/adrv9001_aligner8.v

// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// Redistribution and use of source or resulting binaries, with or without modification
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//      This will allow to generate bit files and not release the source code,
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//
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module adrv9001_aligner8 (
  input             clk,
  input             rst,
  input       [7:0] idata,
  input             ivalid,
  input       [7:0] strobe,
  output reg  [7:0] odata,
  output            ovalid
);

  reg [7:0] idata_d = 'b0;
  reg       ivalid_d = 'b0;

  always @(posedge clk) begin
    if (rst) begin
      idata_d <= 'h0;
    end else if (ivalid) begin
      idata_d <= idata;
    end
    ivalid_d <= ivalid;
  end

  reg [2:0] phase = 'h0;
  always @(posedge clk) begin
    if (rst) begin
      phase <= 0;
    end if (ivalid) begin
      if ((strobe != 'b1111_1111) && (strobe != 'b0000_0000)) begin
        casex (strobe)
          'b1xxx_xxxx : phase <= 0;
          'b01xx_xxxx : phase <= 1;
          'b001x_xxxx : phase <= 2;
          'b0001_xxxx : phase <= 3;
          'b0000_1xxx : phase <= 4;
          'b0000_01xx : phase <= 5;
          'b0000_001x : phase <= 6;
          'b0000_0001 : phase <= 7;
          default     : phase <= phase;
        endcase
      end
    end
  end

  always @(posedge clk) begin
    case (phase)
      0 : odata <= idata_d;
      1 : odata <= {idata_d[6:0],idata[7:7]};
      2 : odata <= {idata_d[5:0],idata[7:6]};
      3 : odata <= {idata_d[4:0],idata[7:5]};
      4 : odata <= {idata_d[3:0],idata[7:4]};
      5 : odata <= {idata_d[2:0],idata[7:3]};
      6 : odata <= {idata_d[1:0],idata[7:2]};
      7 : odata <= {idata_d[0:0],idata[7:1]};
    endcase
  end
  assign ovalid = ivalid_d;

endmodule