pluto_hdl_adi/library/axi_rd_wr_combiner/Makefile

####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := axi_rd_wr_combiner

GENERIC_DEPS += axi_rd_wr_combiner.v

XILINX_DEPS += axi_rd_wr_combiner_ip.tcl

include ../scripts/library.mk
Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface The read and write interfaces of a AXI bus are independent other than that they use the same clock. Yet when connecting a single read-only and a single write-only interface to a Xilinx AXI interconnect it instantiates arbitration logic between the two interfaces. This is dead logic and unnecessarily utilizes the FPGAs resources. Introduce a new helper module that takes a read-only and a write-only AXI interface and combines them into a single read-write interface. The only restriction here is that all three interfaces need to use the same clock. This module is useful for systems which feature a read DMA and a write DMA. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> 2017-03-17 11:48:55 +00:00			`####################################################################################`
Makefiles: Update header with the appropriate license 2021-09-15 15:03:11 +00:00			`## Copyright (c) 2018 - 2021 Analog Devices, Inc.`
			`### SPDX short identifier: BSD-1-Clause`
Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface The read and write interfaces of a AXI bus are independent other than that they use the same clock. Yet when connecting a single read-only and a single write-only interface to a Xilinx AXI interconnect it instantiates arbitration logic between the two interfaces. This is dead logic and unnecessarily utilizes the FPGAs resources. Introduce a new helper module that takes a read-only and a write-only AXI interface and combines them into a single read-write interface. The only restriction here is that all three interfaces need to use the same clock. This module is useful for systems which feature a read DMA and a write DMA. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> 2017-03-17 11:48:55 +00:00			`## Auto-generated, do not modify!`
			`####################################################################################`

Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> 2018-03-23 09:19:51 +00:00			`LIBRARY_NAME := axi_rd_wr_combiner`

Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> 2018-03-27 09:21:09 +00:00			`GENERIC_DEPS += axi_rd_wr_combiner.v`

			`XILINX_DEPS += axi_rd_wr_combiner_ip.tcl`
hdlmake updates 2017-04-25 19:46:26 +00:00
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> 2018-03-23 09:19:51 +00:00			`include ../scripts/library.mk`