pluto_hdl_adi/library/axi_adrv9001/adrv9001_pack.v

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// ***************************************************************************
// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
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// of various HDL (Verilog or VHDL) components. The individual modules are
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`timescale 1ns/100ps

//
// Pack two input beats into one and align it based on start of frame
//
// Frame size 2 beats:
// Temporal ordering of input:
//   idata : MS Beat, LS Beat, MS Beat, LS Beat, ...
//   sof   :       1,       0,       1,       0, ...
// Format of output beats:  {MS Beat, LS Beat}
//
// Frame size 4 beats:
// Temporal ordering of input:
//   idata : MS Beat, LS Beat, MS Beat, LS Beat, MS Beat, LS Beat, ...
//   sof   :       1,       0,       0,       0,       1,       0, ...

module adrv9001_pack #(
  parameter WIDTH = 8
) (
  input                      clk,    // Input clock
  input                      rst,
  input                      sof,    // Start of frame indicator marking the MS Beat
  input       [WIDTH-1:0]    idata,  // Input data beat
  input                      ivalid, // Input data qualifier
  output reg  [WIDTH*2-1:0]  odata,  // Output data beat
  output reg                 ovalid, // Output data qualifier
  output reg                 osof    // Output Start of frame indicator
);

  reg  [WIDTH-1:0] idata_d = {WIDTH{1'b0}};
  always @(posedge clk) begin
    if (ivalid) begin
      idata_d <= idata;
    end
  end

  // Single clock mode:
  reg [6:0] sof_d = 7'b000;
  // Use sof_d[2] for frame size of 4 beats
  // Use sof_d[4,6] for frame size of 8 beats
  always @(posedge clk) begin
    if (rst) begin
      sof_d <= 7'b0;
    end else if (ivalid) begin
      sof_d <= {sof_d[5:0],sof};
    end
    if (ivalid &(sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6])) begin
      odata <= {idata_d,idata};
    end
    ovalid <= ivalid & (sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6]);
    osof <= ivalid & sof_d[0];
  end

endmodule