2018-01-08 16:13:02 +00:00
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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2020-10-09 14:28:10 +00:00
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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2018-01-08 16:13:02 +00:00
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2022-09-23 09:28:22 +00:00
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set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
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2019-06-28 08:41:21 +00:00
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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2022-09-23 09:28:22 +00:00
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
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2019-06-28 08:41:21 +00:00
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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2020-09-28 21:10:35 +00:00
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sysid_gen_sys_init_file
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2019-06-28 08:41:21 +00:00
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2018-01-08 16:13:02 +00:00
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# System clock is 100 MHz for this base design
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set sys_cpu_clk_freq 100
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# ADC external clock generator configurations, the reference clock is the
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# system clock
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# NOTE: For '7 Series' FPGAs the FVCO must be between 600 MHz and 12000 MHz
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set clkgen_vco_div 5
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set clkgen_vco_mul 50
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# specify the external clock rate in MHz (MCLKIN)
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set ext_clk_rate 25
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source ../common/ad7405_bd.tcl
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