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pluto_hdl_adi/projects/common/xilinx/data_offload_bd.tcl

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data_offload: Add integration process for Xilinx carriers
2021-03-15 08:51:14 +00:00
data_offload: Improve external synchronization This commit adds a new synthesis option to the design, that controls whether an internal clock domain crossing will be generated. Disabling this option allows you to use a synchronization signal that is synchronized to the write clock domain externally, and possibly shared between multiple devices. The default value retains the old behavior. Signed-off-by: David Winter <david.winter@analog.com>
2021-08-11 07:59:16 +00:00
proc ad_data_offload_create {instance_name
datapath_type
mem_type
mem_size
source_dwidth
destination_dwidth
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
{axi_data_width 256}
{axi_addr_width 32}
data_offload: Improve external synchronization This commit adds a new synthesis option to the design, that controls whether an internal clock domain crossing will be generated. Disabling this option allows you to use a synchronization signal that is synchronized to the write clock domain externally, and possibly shared between multiple devices. The default value retains the old behavior. Signed-off-by: David Winter <david.winter@analog.com>
2021-08-11 07:59:16 +00:00
{shared_devclk 0}} {
data_offload: Add integration process for Xilinx carriers
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global ad_hdl_dir
global sys_cpu_resetn
create_bd_cell -type hier $instance_name
current_bd_instance /$instance_name
###########################################################################
## Sub-system's ports and interface definitions
###########################################################################
create_bd_pin -dir I -type clk s_axi_aclk
create_bd_pin -dir I -type rst s_axi_aresetn
create_bd_pin -dir I -type clk s_axis_aclk
create_bd_pin -dir I -type rst s_axis_aresetn
create_bd_pin -dir I -type clk m_axis_aclk
create_bd_pin -dir I -type rst m_axis_aresetn
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis
create_bd_pin -dir I init_req
create_bd_pin -dir I sync_ext
ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine Memory requirements are the same as with the dacfifo (1 MiB). Signed-off-by: David Winter <david.winter@analog.com>
2021-04-19 11:58:32 +00:00
set source_addresses [expr ($mem_size * 8) / $source_dwidth]
set source_awidth [log2 $source_addresses]
data_offload: Add integration process for Xilinx carriers
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set destination_max_address [expr ($mem_size * 8) / $destination_dwidth]
set destination_awidth [log2 $destination_max_address]
###########################################################################
# Data offload controller instance
###########################################################################
ad_ip_instance data_offload i_data_offload [list \
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
MEM_TYPE [expr $mem_type == 0 ? 0 : 1] \
MEM_SIZE_LOG2 [log2 $mem_size] \
data_offload: Add integration process for Xilinx carriers
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TX_OR_RXN_PATH $datapath_type \
SRC_DATA_WIDTH $source_dwidth \
DST_DATA_WIDTH $destination_dwidth \
DST_CYCLIC_EN $datapath_type \
data_offload: Improve external synchronization This commit adds a new synthesis option to the design, that controls whether an internal clock domain crossing will be generated. Disabling this option allows you to use a synchronization signal that is synchronized to the write clock domain externally, and possibly shared between multiple devices. The default value retains the old behavior. Signed-off-by: David Winter <david.winter@analog.com>
2021-08-11 07:59:16 +00:00
SYNC_EXT_ADD_INTERNAL_CDC [expr {!$shared_devclk}] \
data_offload: Add integration process for Xilinx carriers
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]
if {$mem_type == 0} {
###########################################################################
# Internal storage instance (BRAMs)
###########################################################################
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
ad_ip_instance util_do_ram storage_unit [list \
SRC_DATA_WIDTH $source_dwidth \
DST_DATA_WIDTH $destination_dwidth \
LENGTH_WIDTH [log2 $mem_size] \
]
data_offload: Add integration process for Xilinx carriers
2021-03-15 08:51:14 +00:00
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
} elseif {$mem_type == 1 || $mem_type == 2} {
data_offload: Add integration process for Xilinx carriers
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###########################################################################
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
# Bridge instance for the external DDR (1) / HBM(2) memory contreller
# NOTE: The DDR/HBM instantiation should be in project's system_bd.tcl file
data_offload: Add integration process for Xilinx carriers
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###########################################################################
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
source $ad_hdl_dir/library/util_hbm/scripts/adi_util_hbm.tcl
ad_create_util_hbm storage_unit \
$datapath_type \
$source_dwidth \
$destination_dwidth \
$mem_size \
$axi_data_width \
$mem_type
if {$mem_type == 1} {
ad_ip_parameter storage_unit CONFIG.AXI_PROTOCOL 0
} else {
ad_ip_parameter storage_unit CONFIG.AXI_PROTOCOL 1
}
data_offload: Add integration process for Xilinx carriers
2021-03-15 08:51:14 +00:00
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
}
data_offload: Add integration process for Xilinx carriers
2021-03-15 08:51:14 +00:00
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
###########################################################################
# Connect Storage to Data Offload
###########################################################################
ad_connect storage_unit/wr_ctrl i_data_offload/wr_ctrl
ad_connect storage_unit/rd_ctrl i_data_offload/rd_ctrl
data_offload: Add integration process for Xilinx carriers
2021-03-15 08:51:14 +00:00
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
ad_connect storage_unit/s_axis i_data_offload/m_storage_axis
ad_connect storage_unit/m_axis i_data_offload/s_storage_axis
data_offload: Add integration process for Xilinx carriers
2021-03-15 08:51:14 +00:00
data_offload: Refactor core Deprecate unused parameters. Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for now. However in the future we might want to add support for non pow2 sizes so register map is not changed. Change transfer length to -1 value to spare logic. Change FIFO interface to AXIS to have backpressure, this allows the implementation of data movement logic in the storage unit and let the FSM handle high level control an synchronization and control the storage unit through a control interface. Refactor FSM to have preparation states where slow storages can be configured and started ahead of the data handling. Make bypasss FIFO optional since in some cases causes timing failures due the missing output register of the memory. This can be targeted in a later commit. Hook up underflow/overflow to regmap useful in case of external memory where rate drops due misconfiguration can be detected. Cleanup for verilator. Scripting: Add HBM and DDR external memory support using util_hbm IP Replace asym_block_ram with util_do_ram IP
2022-02-24 11:44:05 +00:00
ad_connect storage_unit/s_axis_aclk s_axis_aclk
ad_connect storage_unit/s_axis_aresetn s_axis_aresetn
ad_connect storage_unit/m_axis_aclk m_axis_aclk
ad_connect storage_unit/m_axis_aresetn m_axis_aresetn
data_offload: Add integration process for Xilinx carriers
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###########################################################################
# Internal connections
###########################################################################
ad_connect s_axi_aclk i_data_offload/s_axi_aclk
ad_connect s_axi_aresetn i_data_offload/s_axi_aresetn
ad_connect s_axis_aclk i_data_offload/s_axis_aclk
ad_connect s_axis_aresetn i_data_offload/s_axis_aresetn
ad_connect m_axis_aclk i_data_offload/m_axis_aclk
ad_connect m_axis_aresetn i_data_offload/m_axis_aresetn
ad_connect s_axi i_data_offload/s_axi
ad_connect s_axis i_data_offload/s_axis
ad_connect m_axis i_data_offload/m_axis
ad_connect init_req i_data_offload/init_req
ad_connect sync_ext i_data_offload/sync_ext
current_bd_instance /
}
proc log2 {x} {
ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine Memory requirements are the same as with the dacfifo (1 MiB). Signed-off-by: David Winter <david.winter@analog.com>
2021-04-19 11:58:32 +00:00
return [tcl::mathfunc::int [tcl::mathfunc::ceil [expr [tcl::mathfunc::log $x] / [tcl::mathfunc::log 2]]]]
data_offload: Add integration process for Xilinx carriers
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}