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pluto_hdl_adi/projects/daq2/common/daq2_bd.tcl

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daq2: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-23 09:04:47 +00:00
#
# Parameter description:
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_S : Number of samples per frame
#
daq2: rebase conflicts
2014-10-22 20:39:17 +00:00
daq2: Convert to ADI JESD204 Convert the DAQ2 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 09:25:45 +00:00
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
# JESD204B interface configurations
daq2: Convert to ADI JESD204 Convert the DAQ2 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 09:25:45 +00:00
daq2: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-23 09:04:47 +00:00
set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
set TX_SAMPLE_WIDTH 16 ; # N/NP
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
daq2: update adcfifo/dacfifo
2019-01-22 13:19:37 +00:00
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
daq2: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-23 09:04:47 +00:00
set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
daq2: update adcfifo/dacfifo
2019-01-22 13:19:37 +00:00
daq2: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-23 09:04:47 +00:00
set MAX_TX_NUM_OF_LANES 4
set MAX_RX_NUM_OF_LANES 4
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# dac peripherals
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_ip_instance axi_adxcvr axi_ad9144_xcvr [list \
NUM_OF_LANES $TX_NUM_OF_LANES \
QPLL_ENABLE 1 \
TX_OR_RX_N 1 \
]
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
adi_axi_jesd204_tx_create axi_ad9144_jesd $TX_NUM_OF_LANES
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
adi_tpl_jesd204_tx_create axi_ad9144_tpl $TX_NUM_OF_LANES \
$TX_NUM_OF_CONVERTERS \
$TX_SAMPLES_PER_FRAME \
$TX_SAMPLE_WIDTH \
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_ip_instance util_upack2 axi_ad9144_upack [list \
daq2: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-23 09:04:47 +00:00
NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
]
ad_ip_instance axi_dmac axi_ad9144_dma [list \
DMA_TYPE_SRC 0 \
DMA_TYPE_DEST 1 \
ID 1 \
AXI_SLICE_SRC 0 \
AXI_SLICE_DEST 0 \
DMA_LENGTH_WIDTH 24 \
DMA_2D_TRANSFER 0 \
CYCLIC 0 \
DMA_DATA_WIDTH_SRC 128 \
DMA_DATA_WIDTH_DEST $dac_data_width \
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
]
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_data_offload_create axi_ad9144_offload \
1 \
$dac_offload_type \
$dac_offload_size \
$dac_data_width \
$dac_data_width \
daq2: Do not set AXI address width for DO Address size and memory ranges are automatically computed by the external storage interfacing IP (util_hbm) based on the storage size and base address so this parameter is redundant.
2022-04-05 11:20:35 +00:00
$plddr_offload_axi_data_width
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
# synchronization interface
ad_connect axi_ad9144_offload/init_req axi_ad9144_dma/m_axis_xfer_req
ad_connect axi_ad9144_offload/sync_ext GND
daq2: update adcfifo/dacfifo
2019-01-22 13:19:37 +00:00
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# adc peripherals
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_ip_instance axi_adxcvr axi_ad9680_xcvr [list \
NUM_OF_LANES $RX_NUM_OF_LANES \
QPLL_ENABLE 0 \
TX_OR_RX_N 0 \
]
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
adi_axi_jesd204_rx_create axi_ad9680_jesd $RX_NUM_OF_LANES
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
adi_tpl_jesd204_rx_create axi_ad9680_tpl $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
projects:daq2:common: fix adi_tpl_jesd204_rx_create error. (#952) (\ character has to be removed or a blank line inserted before ad_ip_parameter) Fix for : 0b8585a6f commit.
2022-06-06 05:53:07 +00:00
$RX_SAMPLE_WIDTH
PN mismatch DAQ2, DAQ3 and FMCJESDADC1 fix (#950) The AD9680 is a dual 14-bit ADC. Software sets the output format to offset binary before performing the PN tests.
2022-06-02 11:09:36 +00:00
ad_ip_parameter axi_ad9680_tpl/adc_tpl_core CONFIG.CONVERTER_RESOLUTION 14
ad_ip_parameter axi_ad9680_tpl/adc_tpl_core CONFIG.TWOS_COMPLEMENT 0
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_ip_instance util_cpack2 axi_ad9680_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
]
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 17:04:53 +00:00
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_ip_instance axi_dmac axi_ad9680_dma [list \
DMA_TYPE_SRC 1 \
DMA_TYPE_DEST 0 \
ID 0 \
AXI_SLICE_SRC 0 \
AXI_SLICE_DEST 0 \
SYNC_TRANSFER_START 0 \
DMA_LENGTH_WIDTH 24 \
DMA_2D_TRANSFER 0 \
CYCLIC 0 \
DMA_DATA_WIDTH_SRC $adc_data_width \
DMA_DATA_WIDTH_DEST 64 \
]
ad_data_offload_create axi_ad9680_offload \
0 \
$adc_offload_type \
$adc_offload_size \
$adc_data_width \
$adc_data_width \
daq2: Do not set AXI address width for DO Address size and memory ranges are automatically computed by the external storage interfacing IP (util_hbm) based on the storage size and base address so this parameter is redundant.
2022-04-05 11:20:35 +00:00
$plddr_offload_axi_data_width
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
# synchronization interface
ad_connect axi_ad9680_offload/init_req axi_ad9680_dma/s_axis_xfer_req
ad_connect axi_ad9680_offload/sync_ext GND
daq2: update adcfifo/dacfifo
2019-01-22 13:19:37 +00:00
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
# shared transceiver core
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_ip_instance util_adxcvr util_daq2_xcvr [list \
daq2: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-23 09:04:47 +00:00
RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES \
TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES \
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
QPLL_REFCLK_DIV 1 \
QPLL_FBDIV_RATIO 1 \
QPLL_FBDIV 0x30 \
RX_OUT_DIV 1 \
TX_OUT_DIV 1 \
RX_DFE_LPM_CFG 0x0104 \
RX_CDR_CFG 0x0B000023FF10400020 \
]
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
block_design: Updates with new reset net variables
2019-05-30 06:43:44 +00:00
ad_connect $sys_cpu_resetn util_daq2_xcvr/up_rstn
ad_connect $sys_cpu_clk util_daq2_xcvr/up_clk
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
daq2: xcvr pll changes
2016-11-22 17:53:29 +00:00
# reference clocks & resets
create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
projects/- xcvr updates
2016-11-22 21:23:05 +00:00
ad_xcvrpll tx_ref_clk_0 util_daq2_xcvr/qpll_ref_clk_*
ad_xcvrpll rx_ref_clk_0 util_daq2_xcvr/cpll_ref_clk_*
ad_xcvrpll axi_ad9144_xcvr/up_pll_rst util_daq2_xcvr/up_qpll_rst_*
ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_*
daq2: xcvr pll changes
2016-11-22 17:53:29 +00:00
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# connections (dac)
daq2: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-23 09:04:47 +00:00
ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd {0 2 3 1} {} {} $MAX_TX_NUM_OF_LANES
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_tpl/link_clk
ad_connect axi_ad9144_jesd/tx_data axi_ad9144_tpl/link
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/clk
ad_connect axi_ad9144_jesd_rstgen/peripheral_reset axi_ad9144_upack/reset
daq2: Connected loose ad9144 dunf flag that fixes the critical warning
2021-08-19 09:56:56 +00:00
ad_connect axi_ad9144_tpl/dac_dunf axi_ad9144_upack/fifo_rd_underflow
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_connect axi_ad9144_tpl/dac_valid_0 axi_ad9144_upack/fifo_rd_en
for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect axi_ad9144_tpl/dac_enable_$i axi_ad9144_upack/enable_$i
ad_connect axi_ad9144_tpl/dac_data_$i axi_ad9144_upack/fifo_rd_data_$i
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
}
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_connect $sys_cpu_clk axi_ad9144_offload/s_axi_aclk
ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_offload/m_axis_aclk
ad_connect $sys_cpu_clk axi_ad9144_offload/s_axis_aclk
block_design: Updates with new reset net variables
2019-05-30 06:43:44 +00:00
ad_connect $sys_cpu_clk axi_ad9144_dma/m_axis_aclk
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_connect $sys_cpu_resetn axi_ad9144_offload/s_axi_aresetn
ad_connect axi_ad9144_jesd_rstgen/peripheral_aresetn axi_ad9144_offload/m_axis_aresetn
ad_connect $sys_cpu_resetn axi_ad9144_offload/s_axis_aresetn
block_design: Updates with new reset net variables
2019-05-30 06:43:44 +00:00
ad_connect $sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_connect axi_ad9144_upack/s_axis axi_ad9144_offload/m_axis
ad_connect axi_ad9144_offload/s_axis axi_ad9144_dma/m_axis
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# connections (adc)
daq2: Parameterize JESD204 configuration values Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-23 09:04:47 +00:00
ad_xcvrcon util_daq2_xcvr axi_ad9680_xcvr axi_ad9680_jesd {} {} {} $MAX_RX_NUM_OF_LANES
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_tpl/link_clk
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_tpl/link_sof
ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_tpl/link_data
ad_connect axi_ad9680_jesd/rx_data_tvalid axi_ad9680_tpl/link_valid
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_cpack/clk
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/reset
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_connect axi_ad9680_tpl/adc_valid_0 axi_ad9680_cpack/fifo_wr_en
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect axi_ad9680_tpl/adc_enable_$i axi_ad9680_cpack/enable_$i
ad_connect axi_ad9680_tpl/adc_data_$i axi_ad9680_cpack/fifo_wr_data_$i
}
ad_connect axi_ad9680_tpl/adc_dovf axi_ad9680_cpack/fifo_wr_overflow
daq2: Use new pack/unpack infrastructure Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:36:26 +00:00
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_connect $sys_cpu_clk axi_ad9680_offload/s_axi_aclk
ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_offload/s_axis_aclk
ad_connect $sys_cpu_clk axi_ad9680_offload/m_axis_aclk
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_connect $sys_cpu_clk axi_ad9680_dma/s_axis_aclk
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_connect $sys_cpu_resetn axi_ad9680_offload/s_axi_aresetn
ad_connect axi_ad9680_jesd_rstgen/peripheral_aresetn axi_ad9680_offload/s_axis_aresetn
block_design: Updates with new reset net variables
2019-05-30 06:43:44 +00:00
ad_connect $sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_connect $sys_cpu_resetn axi_ad9680_offload/m_axis_aresetn
ad_connect axi_ad9680_cpack/packed_fifo_wr_en axi_ad9680_offload/i_data_offload/s_axis_valid
ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_offload/i_data_offload/s_axis_data
ad_connect axi_ad9680_offload/m_axis axi_ad9680_dma/s_axis
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# interconnect (cpu)
daq2- adxcvr version
2016-07-21 20:08:53 +00:00
ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_cpu_interconnect 0x44A04000 axi_ad9144_tpl
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9144_dma
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_cpu_interconnect 0x7c440000 axi_ad9144_offload
daq2- spi+xcvr address conflict
2016-08-04 14:50:31 +00:00
ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-10 09:25:42 +00:00
ad_cpu_interconnect 0x44A10000 axi_ad9680_tpl
daq2: Convert to ADI JESD204 Convert the DAQ2 project to the ADI JESD204 link layer cores. The change is very straight forward, but a matching change on the software side is required. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-22 09:25:45 +00:00
ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
daq2: Integrate data_offload
2021-03-15 08:51:59 +00:00
ad_cpu_interconnect 0x7c460000 axi_ad9680_offload
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# gt uses hp3, and 100MHz clock for both DRP and AXI4
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9680_xcvr/m_axi
daq2: move gpio/spi to base design
2015-03-09 20:08:25 +00:00
# interconnect (mem/dac)
block_design: Update with new clock net variables Using the new clock net variables in all Xilinx block designs.
2019-05-27 10:04:15 +00:00
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9144_dma/m_src_axi
ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9680_dma/m_dest_axi
daq2: rebase conflicts
2014-10-22 20:39:17 +00:00
daq2: move intrs into ipi
2015-03-12 20:16:55 +00:00
# interrupts
daq2: rebase conflicts
2014-10-22 20:39:17 +00:00
Connect JESD204 interrupts Connect the ADI JESD204 link layer peripheral interrupt signals in all projects. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-02 08:24:37 +00:00
ad_cpu_interrupt ps-10 mb-15 axi_ad9144_jesd/irq
ad_cpu_interrupt ps-11 mb-14 axi_ad9680_jesd/irq
daq2 : Integrate the DACFIFO into the supported projects. + All pack/unpack logic is made by the cpack and upack modules. + The DAC FIFO is integrated between the TX DMA and cpack. + All the top files are updated, all the projects compiled successfully.
2015-05-11 09:17:59 +00:00
ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq