235 lines
8.5 KiB
Coq
235 lines
8.5 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_upack_dsf (
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// dac interface
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dac_clk,
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dac_valid,
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dac_data,
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// dmx interface
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dac_dmx_enable,
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dac_dsf_valid,
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dac_dsf_sync,
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dac_dsf_data);
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// parameters
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parameter P_CNT = 4;
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parameter M_CNT = 8;
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parameter CH_DW = 32;
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parameter CH_OCNT = 4;
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localparam CH_SCNT = CH_DW/16;
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localparam P_WIDTH = CH_DW*P_CNT;
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localparam M_WIDTH = CH_DW*M_CNT;
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localparam O_WIDTH = CH_DW*CH_OCNT;
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localparam E_WIDTH = CH_DW*(M_CNT+1);
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localparam CH_DCNT = P_CNT - CH_OCNT;
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// dac interface
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input dac_clk;
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input dac_valid;
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input [(P_WIDTH-1):0] dac_data;
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// dmx interface
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input dac_dmx_enable;
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output dac_dsf_valid;
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output dac_dsf_sync;
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output [(M_WIDTH-1):0] dac_dsf_data;
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// internal registers
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reg dac_dmx_valid = 'd0;
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reg dac_dsf_valid = 'd0;
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reg dac_dsf_sync = 'd0;
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reg [ 2:0] dac_samples_int = 'd0;
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reg dac_dmx_valid_d = 'd0;
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reg dac_dsf_valid_d = 'd0;
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reg [ 2:0] dac_samples_int_d = 'd0;
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reg [(M_WIDTH-1):0] dac_data_int = 'd0;
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reg [(M_WIDTH-1):0] dac_dsf_data_int = 'd0;
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reg [(M_WIDTH-1):0] dac_dsf_data = 'd0;
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// internal signals
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wire [ 2:0] dac_samples_int_s;
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wire [(E_WIDTH-1):0] dac_data_s;
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wire [(E_WIDTH-1):0] dac_data_int_0_s;
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wire [(E_WIDTH-1):0] dac_data_int_1_s;
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wire [M_WIDTH:0] dac_dsf_data_s;
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// bypass
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generate
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if (CH_OCNT == P_CNT) begin
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assign dac_samples_int_s = 'd0;
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assign dac_data_s = 'd0;
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assign dac_data_int_0_s = 'd0;
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assign dac_data_int_1_s = 'd0;
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assign dac_dsf_data_s[M_WIDTH:P_WIDTH] = 'd0;
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assign dac_dsf_data_s[(P_WIDTH-1):0] = dac_data;
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always @(posedge dac_clk) begin
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dac_dmx_valid <= dac_valid & dac_dmx_enable;
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dac_dsf_valid <= dac_valid & dac_dmx_enable;
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dac_dsf_sync <= dac_valid & dac_dmx_enable;
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dac_samples_int <= 'd0;
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dac_dmx_valid_d <= 'd0;
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dac_dsf_valid_d <= 'd0;
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dac_samples_int_d <= 'd0;
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dac_data_int <= 'd0;
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dac_dsf_data_int <= 'd0;
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if (dac_dmx_enable == 1'b1) begin
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dac_dsf_data <= dac_dsf_data_s[(M_WIDTH-1):0];
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end else begin
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dac_dsf_data <= 'd0;
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end
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end
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end
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endgenerate
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// data store & forward
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generate
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if (P_CNT > CH_OCNT) begin
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assign dac_samples_int_s = (dac_dsf_valid == 1'b1) ? (dac_samples_int + CH_DCNT) :
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((dac_samples_int >= CH_OCNT) ? (dac_samples_int - CH_OCNT) : dac_samples_int);
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always @(posedge dac_clk) begin
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dac_dmx_valid <= dac_valid & dac_dmx_enable;
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if (dac_samples_int_s < CH_OCNT) begin
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dac_dsf_valid <= dac_valid & dac_dmx_enable;
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end else begin
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dac_dsf_valid <= 1'b0;
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end
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if (dac_samples_int_s == 0) begin
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dac_dsf_sync <= dac_valid & dac_dmx_enable;
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end else begin
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dac_dsf_sync <= 1'b0;
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end
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if (dac_dmx_valid == 1'b1) begin
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dac_samples_int <= dac_samples_int_s;
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end
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end
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assign dac_data_s[(E_WIDTH-1):P_WIDTH] = 'd0;
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assign dac_data_s[(P_WIDTH-1):0] = dac_data;
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assign dac_data_int_0_s[(E_WIDTH-1):(E_WIDTH-P_WIDTH)] = dac_data;
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assign dac_data_int_0_s[((E_WIDTH-P_WIDTH)-1):0] =
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dac_data_int[(M_WIDTH-1):(M_WIDTH-(E_WIDTH-P_WIDTH))];
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assign dac_data_int_1_s[(E_WIDTH-1):(E_WIDTH-(M_WIDTH-O_WIDTH))] =
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dac_data_int[((M_WIDTH-O_WIDTH)-1):0];
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assign dac_data_int_1_s[((E_WIDTH-(M_WIDTH-O_WIDTH))-1):0] = 'd0;
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always @(posedge dac_clk) begin
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dac_dmx_valid_d <= dac_dmx_valid;
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dac_dsf_valid_d <= dac_dsf_valid;
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dac_samples_int_d <= dac_samples_int;
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if (dac_dsf_valid_d == 1'b1) begin
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dac_data_int <= dac_data_int_0_s[(E_WIDTH-1):(E_WIDTH-M_WIDTH)];
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end else if (dac_dmx_valid_d == 1'b1) begin
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dac_data_int <= dac_data_int_1_s[(E_WIDTH-1):(E_WIDTH-M_WIDTH)];
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end
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end
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always @(posedge dac_clk) begin
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if (dac_dmx_valid_d == 1'b1) begin
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case (dac_samples_int_d)
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3'b111: dac_dsf_data_int <= { dac_data_s[((CH_DW*1)-1):0],
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dac_data_int[((CH_DW*8)-1):(CH_DW*1)]};
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3'b110: dac_dsf_data_int <= { dac_data_s[((CH_DW*2)-1):0],
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dac_data_int[((CH_DW*8)-1):(CH_DW*2)]};
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3'b101: dac_dsf_data_int <= { dac_data_s[((CH_DW*3)-1):0],
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dac_data_int[((CH_DW*8)-1):(CH_DW*3)]};
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3'b100: dac_dsf_data_int <= { dac_data_s[((CH_DW*4)-1):0],
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dac_data_int[((CH_DW*8)-1):(CH_DW*4)]};
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3'b011: dac_dsf_data_int <= { dac_data_s[((CH_DW*5)-1):0],
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dac_data_int[((CH_DW*8)-1):(CH_DW*5)]};
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3'b010: dac_dsf_data_int <= { dac_data_s[((CH_DW*6)-1):0],
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dac_data_int[((CH_DW*8)-1):(CH_DW*6)]};
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3'b001: dac_dsf_data_int <= { dac_data_s[((CH_DW*7)-1):0],
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dac_data_int[((CH_DW*8)-1):(CH_DW*7)]};
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3'b000: dac_dsf_data_int <= dac_data_s;
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default: dac_dsf_data_int <= 'd0;
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endcase
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end
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end
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end
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endgenerate
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genvar n;
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generate
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if (P_CNT > CH_OCNT) begin
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assign dac_dsf_data_s[M_WIDTH] = 'd0;
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for (n = 0; n < CH_SCNT; n = n + 1) begin: g_out
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assign dac_dsf_data_s[(((n+1)*M_CNT*16)-1):(((n*M_CNT)+CH_OCNT)*16)] = 'd0;
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assign dac_dsf_data_s[((((n*M_CNT)+CH_OCNT)*16)-1):(n*M_CNT*16)] =
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dac_dsf_data_int[(((n+1)*CH_OCNT*16)-1):(n*CH_OCNT*16)];
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end
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end
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endgenerate
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generate
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if (P_CNT > CH_OCNT) begin
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always @(posedge dac_clk) begin
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if (dac_dmx_enable == 1'b1) begin
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dac_dsf_data <= dac_dsf_data_s[(M_WIDTH-1):0];
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end else begin
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dac_dsf_data <= 'd0;
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end
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end
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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