pluto_hdl_adi/projects/daq3/a10gx/Makefile

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## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
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ifeq ($(MMU),)
  MMU := 1
endif

export ALT_NIOS_MMU_ENABLED := $(MMU)

M_DEPS += system_top.v
M_DEPS += system_qsys.tcl
M_DEPS += system_project.tcl
M_DEPS += system_constr.sdc
M_DEPS += ../common/daq3_spi.v
M_DEPS += ../common/daq3_qsys.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
M_DEPS += ../../../library/altera/common/ad_mul.v
M_DEPS += ../../../library/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl
M_DEPS += ../../../library/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl
M_DEPS += ../../../library/altera_avalon_pio/altera_avalon_pio_hw.tcl
M_DEPS += ../../../library/altera_avalon_spi/altera_avalon_spi_hw.tcl
M_DEPS += ../../../library/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl
M_DEPS += ../../../library/altera_avalon_timer/altera_avalon_timer_hw.tcl
M_DEPS += ../../../library/altera_clock_bridge/altera_clock_bridge_hw.tcl
M_DEPS += ../../../library/altera_emif/altera_emif_hw.tcl
M_DEPS += ../../../library/altera_eth_tse/altera_eth_tse_hw.tcl
M_DEPS += ../../../library/altera_iopll/altera_iopll_hw.tcl
M_DEPS += ../../../library/altera_jesd204/altera_jesd204_hw.tcl
M_DEPS += ../../../library/altera_msgdma/altera_msgdma_hw.tcl
M_DEPS += ../../../library/altera_nios2_gen2/altera_nios2_gen2_hw.tcl
M_DEPS += ../../../library/altera_pll_reconfig/altera_pll_reconfig_hw.tcl
M_DEPS += ../../../library/altera_reset_bridge/altera_reset_bridge_hw.tcl
M_DEPS += ../../../library/altera_xcvr_atx_pll_a10/altera_xcvr_atx_pll_a10_hw.tcl
M_DEPS += ../../../library/altera_xcvr_reset_control/altera_xcvr_reset_control_hw.tcl
M_DEPS += ../../../library/axi_ad9152/axi_ad9152.v
M_DEPS += ../../../library/axi_ad9152/axi_ad9152_channel.v
M_DEPS += ../../../library/axi_ad9152/axi_ad9152_core.v
M_DEPS += ../../../library/axi_ad9152/axi_ad9152_hw.tcl
M_DEPS += ../../../library/axi_ad9152/axi_ad9152_if.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
M_DEPS += ../../../library/axi_dmac/2d_transfer.v
M_DEPS += ../../../library/axi_dmac/address_generator.v
M_DEPS += ../../../library/axi_dmac/axi_dmac.v
M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
M_DEPS += ../../../library/axi_dmac/data_mover.v
M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
M_DEPS += ../../../library/axi_dmac/inc_id.h
M_DEPS += ../../../library/axi_dmac/request_arb.v
M_DEPS += ../../../library/axi_dmac/request_generator.v
M_DEPS += ../../../library/axi_dmac/resp.h
M_DEPS += ../../../library/axi_dmac/response_generator.v
M_DEPS += ../../../library/axi_dmac/response_handler.v
M_DEPS += ../../../library/axi_dmac/splitter.v
M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
M_DEPS += ../../../library/common/ad_datafmt.v
M_DEPS += ../../../library/common/ad_dds.v
M_DEPS += ../../../library/common/ad_dds_1.v
M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_jesd_align.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
M_DEPS += ../../../library/common/up_clock_mon.v
M_DEPS += ../../../library/common/up_dac_channel.v
M_DEPS += ../../../library/common/up_dac_common.v
M_DEPS += ../../../library/common/up_delay_cntrl.v
M_DEPS += ../../../library/common/up_xcvr.v
M_DEPS += ../../../library/common/up_xfer_cntrl.v
M_DEPS += ../../../library/common/up_xfer_status.v
M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
M_DEPS += ../../../library/util_axis_fifo/address_gray.v
M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
M_DEPS += ../../../library/util_upack/util_upack.v
M_DEPS += ../../../library/util_upack/util_upack_dmx.v
M_DEPS += ../../../library/util_upack/util_upack_dsf.v
M_DEPS += ../../../library/util_upack/util_upack_hw.tcl


M_ALTERA := quartus_sh --64bit -t 


M_FLIST += *.log
M_FLIST += *_INFO.txt
M_FLIST += *_dump.txt
M_FLIST += db
M_FLIST += *.asm.rpt
M_FLIST += *.done
M_FLIST += *.eda.rpt
M_FLIST += *.fit.*
M_FLIST += *.map.*
M_FLIST += *.sta.*
M_FLIST += *.qsf
M_FLIST += *.qpf
M_FLIST += *.qws
M_FLIST += *.sof
M_FLIST += *.cdf
M_FLIST += *.sld
M_FLIST += *.qdf
M_FLIST += hc_output
M_FLIST += system_bd
M_FLIST += hps_isw_handoff
M_FLIST += hps_sdram_*.csv
M_FLIST += *ddr3_*.csv
M_FLIST += incremental_db
M_FLIST += reconfig_mif
M_FLIST += *.sopcinfo
M_FLIST +=  *.jdi
M_FLIST += *.pin
M_FLIST += *_summary.csv
M_FLIST += *.dpf



.PHONY: all clean clean-all
all: daq3_a10gx.sof



clean:clean-all


clean-all:
	rm -rf $(M_FLIST)


daq3_a10gx.sof: $(M_DEPS)
	-rm -rf $(M_FLIST)
	$(M_ALTERA) system_project.tcl  >> daq3_a10gx_quartus.log 2>&1

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