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pluto_hdl_adi/projects/ad7405_fmc/zed/system_bd.tcl

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ad7405 : Initial commit This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS) reference board.
2018-01-08 16:13:02 +00:00
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;
2020-10-09 14:28:10 +00:00
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
ad7405 : Initial commit This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS) reference board.
2018-01-08 16:13:02 +00:00
system_id: deployed ip
2019-06-28 08:41:21 +00:00
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid: Remove cstring init string
2020-09-28 21:10:35 +00:00
sysid_gen_sys_init_file
system_id: deployed ip
2019-06-28 08:41:21 +00:00
ad7405 : Initial commit This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS) reference board.
2018-01-08 16:13:02 +00:00
# System clock is 100 MHz for this base design
set sys_cpu_clk_freq 100
# ADC external clock generator configurations, the reference clock is the
# system clock
# NOTE: For '7 Series' FPGAs the FVCO must be between 600 MHz and 12000 MHz
set clkgen_vco_div 5
set clkgen_vco_mul 50
# specify the external clock rate in MHz (MCLKIN)
set ext_clk_rate 25
source ../common/ad7405_bd.tcl