36 lines
2.4 KiB
Plaintext
36 lines
2.4 KiB
Plaintext
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FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
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# ad7616 - Parallel mode
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# Note: The design uses an SDP to FMC interposer.
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R19 FMC_LPC_LA10_P DB0 adc_db[0] LVCMOS25 #N/A
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M21 FMC_LPC_LA04_P DB1 adc_db[1] LVCMOS25 #N/A
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R20 FMC_LPC_LA09_P DB2 adc_db[2] LVCMOS25 #N/A
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N22 FMC_LPC_LA03_P DB3 adc_db[3] LVCMOS25 #N/A
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K18 FMC_LPC_LA05_N DB4 adc_db[4] LVCMOS25 #N/A
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P18 FMC_LPC_LA02_N DB5 adc_db[5] LVCMOS25 #N/A
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L22 FMC_LPC_LA06_N DB6 adc_db[6] LVCMOS25 #N/A
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M20 FMC_LPC_LA00_CC_N DB7 adc_db[7] LVCMOS25 #N/A
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J18 FMC_LPC_LA05_P DB8 adc_db[8] LVCMOS25 #N/A
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P17 FMC_LPC_LA02_P DB9 adc_db[9] LVCMOS25 #N/A
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L21 FMC_LPC_LA06_P DB10 adc_db[10] LVCMOS25 #N/A
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M19 FMC_LPC_LA00_CC_P DB11 adc_db[11] LVCMOS25 #N/A
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N20 FMC_LPC_LA01_CC_N DB12 adc_db[12] LVCMOS25 #N/A
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L19 FMC_LPC_CLK0_M2C_N DB13 adc_db[13] LVCMOS25 #N/A
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L18 FMC_LPC_CLK0_M2C_P DB14 adc_db[14] LVCMOS25 #N/A
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N19 FMC_LPC_LA01_CC_P DB15 adc_db[15] LVCMOS25 #N/A
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P22 FMC_LPC_LA03_N SCLK/RDn adc_rd_n LVCMOS25 #N/A
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R21 FMC_LPC_LA09_N WRn adc_wr_n LVCMOS25 #N/A
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A18 FMC_LPC_LA24_P CONVST adc_cnvst LVCMOS25 #N/A
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E20 FMC_LPC_LA21_N CHSEL0 adc_chsel[0] LVCMOS25 #N/A
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E18 FMC_LPC_LA26_N CHSEL1 adc_chsel[1] LVCMOS25 #N/A
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D22 FMC_LPC_LA25_P CHSEL2 adc_chsel[2] LVCMOS25 #N/A
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E19 FMC_LPC_LA21_P HW_RNGSEL0 adc_hw_rngsel[0] LVCMOS25 #N/A
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F18 FMC_LPC_LA26_P HW_RNGSEL1 adc_hw_rngsel[1] LVCMOS25 #N/A
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T19 FMC_LPC_LA10_N BUSY adc_busy LVCMOS25 #N/A
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E21 FMC_LPC_LA27_P SEQEN adc_seq_en LVCMOS25 #N/A
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F19 FMC_LPC_LA22_N RESETn adc_reset_n LVCMOS25 #N/A
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M22 FMC_LPC_LA04_N CSn adc_cs_n LVCMOS25 #N/A
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