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pluto_hdl_adi/projects/common/kcu105/kcu105_system_constr.xdc

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Add copyright and license to .xdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-10 08:38:46 +00:00
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
kcu105: base complete with ethernet errors
2014-04-30 18:40:54 +00:00
# constraints
whitespace: Delete all trailing white spaces
2019-06-05 13:37:34 +00:00
set_property -dict {PACKAGE_PIN AN8 IOSTANDARD LVCMOS18} [get_ports sys_rst]
kcu105: base complete with ethernet errors
2014-04-30 18:40:54 +00:00
# uart
kcu105: sane except for ddr4/ethernet
2014-05-06 19:38:44 +00:00
set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS18} [get_ports uart_sout]
whitespace: Delete all trailing white spaces
2019-06-05 13:37:34 +00:00
set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS18} [get_ports uart_sin]
kcu105: base complete with ethernet errors
2014-04-30 18:40:54 +00:00
whitespace: Delete all trailing white spaces
2019-06-05 13:37:34 +00:00
# ethernet (phy_rst_n automation cannot be used with axi_ethernet 7.0)
kcu105: Don't use phy reset automation, as it's not supported for KCU105
2016-08-08 14:53:32 +00:00
set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS18} [get_ports phy_rst_n]
whitespace: Delete all trailing white spaces
2019-06-05 13:37:34 +00:00
# fan
kcu105: base complete with ethernet errors
2014-04-30 18:40:54 +00:00
whitespace: Delete all trailing white spaces
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set_property -dict {PACKAGE_PIN AJ9 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
kcu105: base complete with ethernet errors
2014-04-30 18:40:54 +00:00
# sw/led
kcu105: gpio led/sw merged to bd default
2015-03-09 20:05:28 +00:00
set_property -dict {PACKAGE_PIN AP8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]]
set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]]
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]]
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]]
set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]]
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]]
set_property -dict {PACKAGE_PIN AN16 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_bd[8]]; ## GPIO_DIP_SW0
set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_bd[9]]; ## GPIO_DIP_SW1
set_property -dict {PACKAGE_PIN AP18 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_bd[10]]; ## GPIO_DIP_SW2
set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_bd[11]]; ## GPIO_DIP_SW3
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_bd[12]]; ## GPIO_SW_N
set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_bd[13]]; ## GPIO_SW_E
set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_bd[14]]; ## GPIO_SW_S
set_property -dict {PACKAGE_PIN AF9 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_bd[15]]; ## GPIO_SW_W
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_bd[16]]; ## GPIO_SW_C
kcu105: base complete with ethernet errors
2014-04-30 18:40:54 +00:00
# iic
whitespace: Delete all trailing white spaces
2019-06-05 13:37:34 +00:00
set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS18} [get_ports iic_scl]
set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports iic_sda]
kcu105: base complete with ethernet errors
2014-04-30 18:40:54 +00:00
kcu105: 2015.2.1 updates
2015-08-25 13:12:32 +00:00
# ddr
set_property -dict {PACKAGE_PIN AK17} [get_ports sys_clk_p]
set_property -dict {PACKAGE_PIN AK16} [get_ports sys_clk_n]
set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 44]
set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 45]
set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 46]
base:constraint: Setting Configuration Bank Voltage Select Set the properties to mirror the hardware configuration so the Vivado tools can provide warnings if there are any conflicts between configuration pin settings, such as an IOSTANDARD on a multi-function configuration pin that conflicts with the configuration voltage. see: https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf The following base constraints were updated: - kcu105 - kc705 - vc707 - ac701
2018-03-02 10:19:36 +00:00
#Setting the Configuration Bank Voltage Select
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
microblaze: add SPI clock constraint The SPI clock is a generated clock from the system clock. Worst case scenario is that the system clock is divided by two.
2019-05-30 08:16:35 +00:00
# Create SPI clock
create_generated_clock -name spi_clk \
-source [get_pins i_system_wrapper/system_i/axi_spi/ext_spi_clk] \
-divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi/sck_o]