284 lines
8.2 KiB
Coq
284 lines
8.2 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top #(
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parameter TX_JESD_L = 4,
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parameter TX_NUM_LINKS = 1,
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parameter RX_JESD_L = 4,
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parameter RX_NUM_LINKS = 1
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) (
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input sys_clk_n,
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input sys_clk_p,
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output ddr4_act_n,
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output [16:0] ddr4_adr,
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output [1:0] ddr4_ba,
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output [1:0] ddr4_bg,
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output ddr4_ck_c,
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output ddr4_ck_t,
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output ddr4_cke,
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output ddr4_cs_n,
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inout [7:0] ddr4_dm_n,
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inout [63:0] ddr4_dq,
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inout [7:0] ddr4_dqs_c,
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inout [7:0] ddr4_dqs_t,
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output ddr4_odt,
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output ddr4_reset_n,
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// GPIOs
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output [3:0] gpio_led,
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input [3:0] gpio_dip_sw,
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input [1:0] gpio_pb,
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// FMC HPC IOs
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input [1:0] agc0,
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input [1:0] agc1,
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input [1:0] agc2,
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input [1:0] agc3,
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input clkin6_n,
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input clkin6_p,
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input clkin10_n,
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input clkin10_p,
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input fpga_refclk_in_n,
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input fpga_refclk_in_p,
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input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n,
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input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p,
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output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n,
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output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p,
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input [TX_NUM_LINKS-1:0] fpga_syncin_n,
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input [TX_NUM_LINKS-1:0] fpga_syncin_p,
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output [RX_NUM_LINKS-1:0] fpga_syncout_n,
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output [RX_NUM_LINKS-1:0] fpga_syncout_p,
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inout [10:0] gpio,
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inout hmc_gpio1,
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output hmc_sync,
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input [1:0] irqb,
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output rstb,
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output [1:0] rxen,
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output spi0_csb,
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input spi0_miso,
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output spi0_mosi,
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output spi0_sclk,
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output spi1_csb,
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output spi1_sclk,
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inout spi1_sdio,
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input sysref2_n,
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input sysref2_p,
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output [1:0] txen
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);
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// internal signals
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wire [95:0] gpio_i;
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wire [95:0] gpio_o;
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wire [95:0] gpio_t;
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wire [ 2:0] spi0_csn;
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wire [ 2:0] spi1_csn;
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wire spi1_mosi;
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wire spi1_miso;
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wire sysref;
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wire [TX_NUM_LINKS-1:0] tx_syncin;
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wire [RX_NUM_LINKS-1:0] rx_syncout;
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wire [7:0] rx_data_p_loc;
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wire [7:0] rx_data_n_loc;
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wire [7:0] tx_data_p_loc;
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wire [7:0] tx_data_n_loc;
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wire clkin6;
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wire clkin10;
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wire tx_device_clk;
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wire rx_device_clk;
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// instantiations
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IBUFDS i_ibufds_sysref (
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.I (sysref2_p),
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.IB (sysref2_n),
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.O (sysref));
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IBUFDS i_ibufds_tx_device_clk (
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.I (clkin6_p),
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.IB (clkin6_n),
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.O (clkin6));
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IBUFDS i_ibufds_rx_device_clk (
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.I (clkin10_p),
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.IB (clkin10_n),
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.O (clkin10));
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genvar i;
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generate
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for(i=0;i<TX_NUM_LINKS;i=i+1) begin : g_tx_buffers
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IBUFDS i_ibufds_syncin (
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.I (fpga_syncin_p[i]),
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.IB (fpga_syncin_n[i]),
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.O (tx_syncin[i]));
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end
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for(i=0;i<RX_NUM_LINKS;i=i+1) begin : g_rx_buffers
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OBUFDS i_obufds_syncout (
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.I (rx_syncout[i]),
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.O (fpga_syncout_p[i]),
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.OB (fpga_syncout_n[i]));
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end
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endgenerate
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BUFG i_tx_device_clk (
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.I (clkin6),
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.O (tx_device_clk)
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);
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BUFG i_rx_device_clk (
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.I (clkin10),
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.O (rx_device_clk)
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);
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// spi
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assign spi0_csb = spi0_csn[0];
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assign spi1_csb = spi1_csn[0];
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ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi (
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.spi_csn (spi1_csn[0]),
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.spi_clk (spi1_sclk),
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.spi_mosi (spi1_mosi),
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.spi_miso (spi1_miso),
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.spi_sdio (spi1_sdio),
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.spi_dir ());
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// gpios
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ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
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.dio_t (gpio_t[43:32]),
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.dio_i (gpio_o[43:32]),
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.dio_o (gpio_i[43:32]),
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.dio_p ({hmc_gpio1, // 43
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gpio[10:0]})); // 42-32
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assign gpio_i[44] = agc0[0];
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assign gpio_i[45] = agc0[1];
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assign gpio_i[46] = agc1[0];
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assign gpio_i[47] = agc1[1];
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assign gpio_i[48] = agc2[0];
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assign gpio_i[49] = agc2[1];
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assign gpio_i[50] = agc3[0];
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assign gpio_i[51] = agc3[1];
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assign gpio_i[52] = irqb[0];
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assign gpio_i[53] = irqb[1];
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assign hmc_sync = gpio_o[54];
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assign rstb = gpio_o[55];
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assign rxen[0] = gpio_o[56];
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assign rxen[1] = gpio_o[57];
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assign txen[0] = gpio_o[58];
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assign txen[1] = gpio_o[59];
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/* Board GPIOS. Buttons, LEDs, etc... */
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assign gpio_led = gpio_o[3:0];
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assign gpio_i[3:0] = gpio_o[3:0];
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assign gpio_i[7: 4] = gpio_dip_sw;
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assign gpio_i[9: 8] = gpio_pb;
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// Unused GPIOs
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assign gpio_i[94:54] = gpio_o[94:54];
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assign gpio_i[31:10] = gpio_o[31:10];
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system_wrapper i_system_wrapper (
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.gpio0_i (gpio_i[31:0]),
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.gpio0_o (gpio_o[31:0]),
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.gpio0_t (gpio_t[31:0]),
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.gpio1_i (gpio_i[63:32]),
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.gpio1_o (gpio_o[63:32]),
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.gpio1_t (gpio_t[63:32]),
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.gpio2_i (gpio_i[95:64]),
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.gpio2_o (gpio_o[95:64]),
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.gpio2_t (gpio_t[95:64]),
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.ddr4_dimm1_sma_clk_clk_n (sys_clk_n),
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.ddr4_dimm1_sma_clk_clk_p (sys_clk_p),
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.ddr4_dimm1_act_n (ddr4_act_n),
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.ddr4_dimm1_adr (ddr4_adr),
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.ddr4_dimm1_ba (ddr4_ba),
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.ddr4_dimm1_bg (ddr4_bg),
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.ddr4_dimm1_ck_c (ddr4_ck_c),
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.ddr4_dimm1_ck_t (ddr4_ck_t),
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.ddr4_dimm1_cke (ddr4_cke),
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.ddr4_dimm1_cs_n (ddr4_cs_n),
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.ddr4_dimm1_dm_n (ddr4_dm_n),
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.ddr4_dimm1_dq (ddr4_dq),
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.ddr4_dimm1_dqs_c (ddr4_dqs_c),
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.ddr4_dimm1_dqs_t (ddr4_dqs_t),
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.ddr4_dimm1_odt (ddr4_odt),
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.ddr4_dimm1_reset_n (ddr4_reset_n),
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.spi0_csn (spi0_csn),
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.spi0_miso (spi0_miso),
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.spi0_mosi (spi0_mosi),
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.spi0_sclk (spi0_sclk),
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.spi1_csn (spi1_csn),
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.spi1_miso (spi1_miso),
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.spi1_mosi (spi1_mosi),
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.spi1_sclk (spi1_sclk),
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// FMC HPC
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// TODO: Max 4 lanes
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.GT_Serial_0_gtx_p (tx_data_p_loc[3:0]),
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.GT_Serial_0_gtx_n (tx_data_n_loc[3:0]),
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.GT_Serial_0_grx_p (rx_data_p_loc[3:0]),
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.GT_Serial_0_grx_n (rx_data_n_loc[3:0]),
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.gt_bridge_ip_0_diff_gt_ref_clock_0_clk_p(fpga_refclk_in_p),
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.gt_bridge_ip_0_diff_gt_ref_clock_0_clk_n(fpga_refclk_in_n),
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.rx_device_clk (rx_device_clk),
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.tx_device_clk (tx_device_clk),
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.rx_sync_0 (rx_syncout),
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.tx_sync_0 (tx_syncin),
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.rx_sysref_0 (sysref),
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.tx_sysref_0 (sysref)
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);
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assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
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assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];
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assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
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assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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