pluto_hdl_adi/library/altera/common/ad_lvds_clk.v

83 lines
2.7 KiB
Coq
Raw Normal View History

// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_clk #(
parameter DEVICE_TYPE = 0) (
2016-05-04 17:37:22 +00:00
input rst,
output locked,
input clk_in_p,
input clk_in_n,
output clk);
2016-05-04 17:37:22 +00:00
2016-04-28 19:46:27 +00:00
// instantiations
generate
if (DEVICE_TYPE == 0) begin
2016-04-28 19:46:27 +00:00
alt_clk i_clk (
2016-05-04 17:37:22 +00:00
.rst (rst),
2016-04-28 19:46:27 +00:00
.refclk (clk_in_p),
.outclk_0 (clk),
2016-05-04 17:37:22 +00:00
.locked (locked));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altera_pll #(
.reference_clock_frequency("250.0 MHz"),
.operation_mode("lvds"),
.number_of_clocks(1),
.output_clock_frequency0("250.0 MHz"),
.phase_shift0("0"))
i_clk (
.rst (rst),
.refclk (clk_in_p),
.outclk (clk),
.locked (locked));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************