276 lines
13 KiB
ReStructuredText
276 lines
13 KiB
ReStructuredText
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.. _axi_pwm_gen:
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AXI PWM Generator
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================================================================================
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.. hdl-component-diagram::
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The :git-hdl:`AXI PWM Generator <library/axi_pwm_gen>` core is used to generate
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a maximum of 16 configurable signals (Pulse-Width Modulations).
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The pulses are generated according to the state of a counter;
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there is one counter for each pulse.
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Features
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--------------------------------------------------------------------------------
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* Up to 16 configurable signals (period, width, offset)
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* External synchronization
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* External clock
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/axi_pwm_gen/axi_pwm_gen.sv`
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- SystemVerilog source for the top module
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* - :git-hdl:`library/axi_pwm_gen/axi_pwm_gen_1.v`
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- Verilog source for a channel module
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* - :git-hdl:`library/axi_pwm_gen/axi_pwm_gen_regmap.sv`
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- SystemVerilog source for regmap
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* - :git-hdl:`library/axi_pwm_gen/axi_pwm_gen_constr.ttcl`
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- Dynamic constraint file (AMD tools)
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* - :git-hdl:`library/axi_pwm_gen/axi_pwm_gen_constr.sdc`
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- Constraint file (Intel tools)
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* - :git-hdl:`library/axi_pwm_gen/axi_pwm_gen_ip.tcl`
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- IP definition file (AMD tools)
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* - :git-hdl:`library/axi_pwm_gen/axi_pwm_gen_hw.tcl`
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- IP definition file (Intel tools)
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Block Diagram
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--------------------------------------------------------------------------------
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.. image:: block_diagram.svg
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:alt: AXI PWM Generator block diagram
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. note::
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The pulse period, width and offset are set in number of clock cycles.
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The clock is the axi clock or if activated, the external clock.
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.. hdl-parameters::
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* - ID
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- Core ID should be unique for each IP in the system.
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* - ASYNC_CLK_EN
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- Use external clock, asynchronous to s_axi_aclk.
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* - N_PWMS
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- Number of pulses/pwms.
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* - PWM_EXT_SYNC
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- PWM offset counter uses external sync.
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* - EXT_ASYNC_SYNC
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- The external sync for pulse 0 is asynchronous.
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* - SOFTWARE_BRINGUP
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- Require software, to bring the core out if reset
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* - EXT_SYNC_PHASE_ALIGN
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- Set default flag value for external sync phase align feature
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* - FORCE_ALIGN
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- Set default flag value for force align feature
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* - START_AT_SYNC
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- Set default flag value for start at sync feature
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.. _axi_pwm_gen interface:
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Interface
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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* - ext_clk
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- External clock.
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* - ext_sync
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- External sync signal, synchronizes pulses to an external signal.
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* - pwm_*
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- Output PWM, up to 16, indexed from 0 to 15.
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Detailed Description
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--------------------------------------------------------------------------------
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Let's start with some base notions:
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- The pulse generators are based on incrementing counters.
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- The pulse period starts on the high level interval and ends on the low level.
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- By default, all counters start at the same time. When a different phase (delay)
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is needed between the pulses, we can set an offset.
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- The offset feature can synchronize channels 0 to 15 relative to an offset
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counter.
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- The offset counter will wait for a HIGH -> LOW transition of the
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synchronization pulse (''load_config'' or ''ext_sync'').
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For more info see the below channel phase alignment feature.
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- To **disable a PWM channel**, write 0 to its ``period`` register.
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- The duty cycle is the ratio between pulse width over pulse period.
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The following features can be enabled by setting a flag in the
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register REG_UP_CONTROL(0x18):
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Channel phase alignment
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The AXI PWM Generator core can be synchronized by an external signal on the
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HIGH -> LOW transition of the ext_sync signal.
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The external sync can be used in two modes, based on the external sync align
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feature.
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- external_sync_align flag is set(1) the ext_sync will trigger a phase align
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at each neg-edge.
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- otherwise the phase align must be armed by a load config toggle, while
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the external sync must be held HIGH.
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Software bringup (software reset)
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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If set, the software must bring the core out of reset, after a system reset,
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for the pwm signals to be generated.
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Force align
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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If set, the current active pulses are immediately stopped and realigned.
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Otherwise, the synchronized pulses will start only after all running pulse
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periods end. Software overwritable at runtime.
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Start at sync
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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If active, the pulses will start after the trigger event.
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Otherwise each pulse will start after a period equal to the one for which
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it is set. Software over writable at runtime.
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This flags are software overwritable at runtime. Default value is given at build time.
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- software bringup = 1
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- start at sync = 1
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- force align = 0
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- ext sync align = 0
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Timing Diagrams and examples
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--------------------------------------------------------------------------------
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The timing diagram below, shows the ``load_config`` functionality with
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force sync and force start disabled.
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.. wavedrom::
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{ "signal" : [
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{ "name": "clk", "wave": "P.............................."},
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{ "name": "pwm_1 period", "wave": "9.............9................","data":["8","10"]},
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{ "name": "pwm_1 pulse", "wave": "9.............9................","data":["3","5"]},
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{ "name": "pwm_1 offset", "wave": "9.............9................","data":["1","0"]},
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{ "name": "pwm_2 period", "wave": "6.............6................","data":["8","10"]},
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{ "name": "pwm_2 pulse", "wave": "6.............6................","data":["3","5"]},
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{ "name": "pwm_2 offset", "wave": "6.............6................","data":["5","4"]},
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{ "name": "load_config", "wave": "0............10................",phase: 0,},
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{ "name": "offset counter", "wave": "7777777777777777777777777777777","data":["55","56","57","58","59","60","61","62","63","64","65","66","67","68","0","1","2","3","4","5","6","7","8","9","10","11","12","13","14","15","16"]},
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{ "name": "counter 0", "wave": "45555555544444=6666666666333333","data":["8","1","2","3","4","5","6","7","8","1","2","3","4","5","1","1","2","3","4","5","6","7","8","9","10","1","2","3","4","5","6"]},
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{ "name": "pwm 0", "wave": "lh..l....h...l.h....l....h....l"},
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{ "name": "counter 1", "wave": "44444555555554=...6666666666333","data":["4","5","6","7","8","1","2","3","4","5","6","7","8","1","1","1","2","3","4","5","6","7","8","9","10","1","2","3","4","5"]},
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{ "name": "pwm 1", "wave": "l....h..l....hl...h....l....h.."},
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],
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foot: {text: ['tspan', 'load_config force_sync and start at sync e.g.'],
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}}
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The timing diagram below, shows the ``load_config`` functionality with
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force sync disabled and force start enabled.
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.. wavedrom::
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{ "signal" : [
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{ "name": "clk", "wave": "P.............................."},
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{ "name": "pwm_1 period", "wave": "9...........9..................","data":["8","10"]},
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{ "name": "pwm_1 pulse", "wave": "9...........9..................","data":["3","5"]},
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{ "name": "pwm_1 offset", "wave": "9...........9..................","data":["1","0"]},
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{ "name": "pwm_2 period", "wave": "6...........6..................","data":["8","10"]},
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{ "name": "pwm_2 pulse", "wave": "6...........6..................","data":["3","5"]},
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{ "name": "pwm_2 offset", "wave": "6...........6..................","data":["5","4"]},
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{ "name": "load_config", "wave": "0..........10..................",phase: 0,},
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{ "name": "offset counter", "wave": "7777777777777777777777777777777","data":["55","56","57","58","59","60","61","62","63","64","65","66","67","68","0","1","2","3","4","5","6","7","8","9","10","11","12","13","14","15","16"]},
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{ "name": "counter 0", "wave": "45555555544444444=6666666666333","data":["8","1","2","3","4","5","6","7","8","1","2","3","4","5","6","7","8","1","1","2","3","4","5","6","7","8","9","10","1","2","3"]},
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{ "name": "pwm 0", "wave": "lh..l....h...l....h....l....h.."},
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{ "name": "counter 1", "wave": "4444455555555=.......6666666666","data":["4","5","6","7","8","1","2","3","4","5","6","7","8","1","1","2","3","4","5","6","7","8","9","10"]},
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{ "name": "pwm 1", "wave": "l....h..l............h....l...."},
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],
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foot: {text: ['tspan', 'load_config with start at sync(default)'],
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}}
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The timing diagram below, shows the ``load_config`` functionality with
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force sync and force start enabled.
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.. wavedrom::
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{ "signal" : [
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{ "name": "clk", "wave": "P.............................."},
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{ "name": "pwm_1 period", "wave": "9.............9................","data":["8","10"]},
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{ "name": "pwm_1 pulse", "wave": "9.............9................","data":["3","5"]},
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{ "name": "pwm_1 offset", "wave": "9.............9................","data":["1","0"]},
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{ "name": "pwm_2 period", "wave": "6.............6................","data":["8","10"]},
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{ "name": "pwm_2 pulse", "wave": "6.............6................","data":["3","5"]},
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{ "name": "pwm_2 offset", "wave": "6.............6................","data":["5","4"]},
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{ "name": "load_config", "wave": "0............10................",phase: 0,},
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{ "name": "offset counter", "wave": "7777777777777777777777777777777","data":["55","56","57","58","59","60","61","62","63","64","65","66","67","68","0","1","2","3","4","5","6","7","8","9","10","11","12","13","14","15","16"]},
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{ "name": "counter 0", "wave": "45555555544444=6666666666333333","data":["8","1","2","3","4","5","6","7","8","1","2","3","4","5","1","1","2","3","4","5","6","7","8","9","10","1","2","3","4","5","6"]},
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{ "name": "pwm 0", "wave": "lh..l....h...l.h....l....h....l"},
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{ "name": "counter 1", "wave": "44444555555554=...6666666666333","data":["4","5","6","7","8","1","2","3","4","5","6","7","8","1","1","1","2","3","4","5","6","7","8","9","10","1","2","3","4","5"]},
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{ "name": "pwm 1", "wave": "l....h..l....hl...h....l....h.."},
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],
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foot: {text: ['tspan', 'load_config force_sync and start at sync e.g.'],
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}}
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The below timing diagrams, shows the ``external_sync`` functionality:
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.. wavedrom::
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{ "signal" : [
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{ "name": "clk", "wave": "P............................"},
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{ "name": "pwm_1 period", "wave": "9............................","data":["8"]},
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{ "name": "pwm_1 pulse", "wave": "9............................","data":["3"]},
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{ "name": "pwm_1 offset", "wave": "9............................","data":["1"]},
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{ "name": "pwm_2 period", "wave": "6............................","data":["8"]},
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{ "name": "pwm_2 pulse", "wave": "6............................","data":["3"]},
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{ "name": "pwm_2 offset", "wave": "6............................","data":["5"]},
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{ "name": "external_sync", "wave": "1....0.......................",phase: 0.5,},
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{ "name": "offset counter", "wave": "=.....7777777777777777777777=","data":["0","1","2","3","4","5","6","7","8","9","10","11","12","13","14","15","16","17","18","19","20","21","22"]},
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{ "name": "counter 0", "wave": "=......444444455555555444444=","data":["1","2","3","4","5","6","7","8","1","2","3","4","5","6","7","8","1","2","3","4","5","6"]},
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{ "name": "pwm 0", "wave": "l......h..l....h..l....h..l.."},
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{ "name": "counter 1", "wave": "=..........44444445555555544=","data":["1","2","3","4","5","6","7","8","1","2","3","4","5","6","7","8","1","2"]},
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{ "name": "pwm 1", "wave": "l..........h..l....h..l....h."},
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],
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foot: {text: ['tspan', 'External sync, start at sync (default) e.g.'],
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}}
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.. wavedrom::
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{ "signal" : [
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{ "name": "clk", "wave": "P............................"},
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{ "name": "pwm_1 period", "wave": "9............................","data":["8"]},
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{ "name": "pwm_1 pulse", "wave": "9............................","data":["3"]},
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{ "name": "pwm_1 offset", "wave": "9............................","data":["1"]},
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{ "name": "pwm_2 period", "wave": "6............................","data":["8"]},
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{ "name": "pwm_2 pulse", "wave": "6............................","data":["3"]},
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{ "name": "pwm_2 offset", "wave": "6............................","data":["5"]},
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{ "name": "external_sync", "wave": "1....0.......................",phase: 0.5,},
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{ "name": "offset counter", "wave": "=.....7777777777777777777777=","data":["0","1","2","3","4","5","6","7","8","9","10","11","12","13","14","15","16","17","18","19","20","21","22"]},
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{ "name": "counter 0", "wave": "=......444444455555555444444=","data":["1","2","3","4","5","6","7","8","1","2","3","4","5","6","7","8","1","2","3","4","5","6"]},
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{ "name": "pwm 0", "wave": "l.............h..l....h..l..."},
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{ "name": "counter 1", "wave": "=..........44444445555555544=","data":["1","2","3","4","5","6","7","8","1","2","3","4","5","6","7","8","1","2"]},
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{ "name": "pwm 1", "wave": "l.................h..l....h.."},
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],
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foot: {text: ['tspan', 'External sync without start at sync e.g.'],
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}}
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Register Map
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--------------------------------------------------------------------------------
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.. hdl-regmap::
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:name: axi_pwm_gen
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