346 lines
12 KiB
ReStructuredText
346 lines
12 KiB
ReStructuredText
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.. _pulsar_lvds:
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PULSAR-LVDS HDL project
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==================================================================================
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Overview
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----------------------------------------------------------------------------------
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The :adi:`AD7625`, :adi:`AD7626`, :adi:`AD7960`, :adi:`AD7961` devices are parts
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from ADC LVDS PulSAR family.
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The :adi:`AD7625` / :adi:`AD7626` is a 16-bit, 6 MSPS / 10 MSPS, charge
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redistribution successive approximation register (SAR) architecture,
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analog to-digital converter (ADC). SAR architecture allows unmatched performance
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both in noise (92dB SNR) and in linearity (±1 LSB INL / ±0.45 LSB INL). The
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AD7626 contains a high speed 16-bit sampling ADC, an internal conversion clock,
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and an internal buffered reference. On the CNV edge, it samples the voltage
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difference between IN+ and IN- pins. The voltages on these pins swing in opposite
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phase between 0 V and REF.
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The 4.096V reference voltage, REF, can be generated internally or applied
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externally. All converted results are available on a single LVDS self-clocked or
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echoed-clock serial interface reducing external hardware connections. The
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:adi:`AD7625` / :adi:`AD7626` is available in a 32-lead LFCSP (5mm by 5mm) with
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operation specified from -40°C to +85°C.
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The :adi:`AD7960` / :adi:`AD7961` is an 18-bit/16-bit, 5 MSPS, charge
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redistribution successive approximation (SAR), analog-to-digital converter (ADC).
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The SAR architecture allows unmatched performance both in noise and in linearity.
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The :adi:`AD7960` / :adi:`AD7961` contains a low power, high speed, 18-bit/16-bit
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sampling ADC, an internal conversion clock, and an internal reference buffer.
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On the CNV± edge, the :adi:`AD7960` / :adi:`AD7961` samples the voltage
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difference between the IN+ and IN− pins. The voltages on these pins swing in
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opposite phase between 0 V and 4.096 V and between 0 V and 5 V. The reference
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voltage is applied to the part externally. All conversion results are available
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on a single LVDS self clocked or echoed clock serial interface. The AD7960 is
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available in a 32-lead LFCSP (QFN) with operation specified from −40°C to +85°C.
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Applications:
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* Digital imaging systems
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* High speed data acquisition
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* High dynamic range telecommunications receivers
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* Spectrum analysis
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* Test equipment
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Supported boards
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-------------------------------------------------------------------------------
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- :adi:`EVAL-AD7625-FMCZ <AD7625>`
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- :adi:`EVAL-AD7626-FMCZ <AD7626>`
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- :adi:`EVAL-AD7960-FMCZ <AD7960>`
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- :adi:`EVAL-AD7961-FMCZ <AD7961>`
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Supported devices
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-------------------------------------------------------------------------------
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- :adi:`AD7625`
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- :adi:`AD7626`
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- :adi:`AD7960`
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- :adi:`AD7961`
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- :adi:`ADR3412`
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- :adi:`ADR4520`
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- :adi:`AD74540`
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- :adi:`AD4550`
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- :adi:`AD8031`
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- :adi:`ADA4899-1`
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- :adi:`ADA4897-1`
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- :adi:`ADP7102`
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- :adi:`ADP7104`
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- :adi:`ADP124`
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- :adi:`ADP2300`
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Supported carriers
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-------------------------------------------------------------------------------
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- :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>` on FMC slot
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Block design
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-------------------------------------------------------------------------------
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagram:
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.. image:: pulsar_lvds_block_diagram.svg
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:width: 800
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:align: center
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:alt: PulSAR LVDS block diagram
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Configuration modes
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The RESOLUTION_16_18N configuration parameter defines the resolution of the ADC
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(16 or 18 bits). By default it is set to 0. Depending of the project, some
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hardware modifications need to be done on the board and/or make command:
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In case of the **AD7960** project:
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.. code-block::
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make RESOLUTION_16_18N=0
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In case of the **AD7625/AD7626/AD7961** project:
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.. code-block::
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make RESOLUTION_16_18N=1
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Jumper setup AD7625/AD7626
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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================== ================= ===========================================
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Jumper/Solder link Default Position Description
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================== ================= ===========================================
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LK2 Inserted Connects REFIN to the 1.2V external
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reference.
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LK3 Inserted Connects the 4.096 V output from the
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:adi:`ADR4540` after buffer :adi:`AD8031`
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solution.
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LK6 B Connects the output of the VCM buffer to
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the VCM of the amplifier.
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LK9 A Connects to the 7 V supply coming from
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the :adi:`ADP7102`.
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LK10 A Connects to the −2.5 V coming from the
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:adi:`ADP2300`.
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JP1,JP2 B Connects CNV+ and CNV− from the FPGA.
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JP6 B Connects 7 V to amplifier +VS.
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JP10 B Connects −2.5 V to amplifier −VS.
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JP11,JP12 B Connect outputs from the :adi:`ADA4899-1`
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to the inputs of the ADC.
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JP13,JP14 B Connect outputs from the :adi:`ADA4899-1`
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to the inputs of the ADC.
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================== ================= ===========================================
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Jumper setup AD7960/AD7961
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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================== ================= ============================================
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Jumper/Solder link Default Position Description
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================== ================= ============================================
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LK2,LK3 Inserted Option to use external amplifier supplies
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+ VS and – VS.
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LK4 Inserted Connects to +7 V coming from :adi:`ADP7102`.
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LK5 B Connects to −2.5 V coming from
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:adi:`ADP2300`.
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LK6 B Connects the output of VCM buffer to VCM
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of amplifier.
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LK7 B Connects the +5 V output from
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:adi:`ADR4550` to REF buffer AD8031.
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JP1,JP2 B Connects analog inputs VIN+ and VIN− to
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the inputs of the ADC driver.
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:adi:`ADA4899-1` or :adi:`ADA4897-1`.
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JP3,JP4 B Connect outputs from :adi:`ADA4899-1`
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to inputs of :adi:`AD7960`.
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JP5 A Connect the VCM output from :adi:`AD7960`
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to :adi:`AD8031`.
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JP7 A Connects REFIN to 2.048 V external
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reference.
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JP8 B Connects +7 V to amplifier +VS.
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JP9 B Connects −2.5 V to amplifier −VS.
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================== ================= ============================================
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL (see more at :ref:`architecture`).
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======================== ===========
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Instance Address
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======================== ===========
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axi_pulsar_lvds 0x44A0_0000
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axi_pulsar_lvds_dma 0x44A3_0000
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axi_pwm_gen 0x44A6_0000
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reference_clkgen 0x44A8_0000
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======================== ===========
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I2C connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 20 20 20 20 20
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:header-rows: 1
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* - I2C type
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- I2C manager instance
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- Alias
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- Address
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- I2C subordinate
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* - PL
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- iic_fmc
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- axi_iic_fmc
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- 0x4162_0000
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- ---
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* - PL
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- iic_main
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- axi_iic_main
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- 0x4160_0000
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- ---
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GPIOs
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The Software GPIO number is calculated as follows:
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- Zynq-7000: if PS7 is used, then offset is 54
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 2
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* - GPIO signal
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- Direction
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- HDL GPIO EMIO
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- Software GPIO
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* -
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- (from FPGA view)
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-
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- Zynq-7000
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* - en3_fmc **
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- INOUT
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- 35
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- 89
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* - en2_fmc **
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- INOUT
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- 34
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- 88
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* - en1_fmc
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- INOUT
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- 33
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- 87
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* - en0_fmc
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- INOUT
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- 32
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- 86
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.. admonition:: Legend
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:class: note
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- ``**`` instantiated only for AD7960/AD7961
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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=============== === ========== ===========
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Instance name HDL Linux Zynq Actual Zynq
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=============== === ========== ===========
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axi_ad7616_dma 13 57 89
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=============== === ========== ===========
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Building the HDL project
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-------------------------------------------------------------------------------
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The design is built upon ADI's generic HDL reference design framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here </>`. To get
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the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository, and then build the project as follows:
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**Linux/Cygwin/WSL**
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.. code-block::
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:linenos:
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user@analog:~$ cd hdl/projects/pulsar_lvds_adc/zed
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user@analog:~/hdl/projects/pulsar_lvds_adc/zed$ make RESOLUTION_16_18N=0
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The result of the build, if parameters were used, will be in a folder named
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by the configuration used:
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if the following command was run
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``make RESOLUTION_16_18N=0``
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then the folder name will be:
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``RESOLUTION_16_18N0``
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A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
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Resources
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-------------------------------------------------------------------------------
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Product datasheets:
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- :adi:`AD7625`
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- :adi:`AD7626`
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- :adi:`AD7960`
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- :adi:`AD7961`
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- :adi:`UG-745, Evaluation Board User Guide <media/en/technical-documentation/user-guides/EVAL-AD7625FMCZ_7626FMCZ_UG-745.pdf>`
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- :adi:`UG-490, Evaluation Board User Guide <media/en/technical-documentation/user-guides/UG-490.pdf>`
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- :adi:`UG-581, Evaluation Board User Guide <media/en/technical-documentation/user-guides/ug-581.pdf>`
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`PULSAR_LVDS HDL project source code <projects/pulsar_lvds_adc>`
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.. list-table::
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:widths: 30 35 35
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:header-rows: 1
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* - IP name
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- Source code link
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- Documentation link
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* - AXI_PULSAR_LVDS
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- :git-hdl:`library/axi_pulsar_lvds <library/axi_pulsar_lvds>`
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- ---
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* - AXI_CLKGEN
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- :git-hdl:`library/axi_clkgen <library/axi_clkgen>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac <library/axi_dmac>`
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- :ref:`here <axi_dmac>`
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* - AXI_HDMI_TX
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- :git-hdl:`library/axi_hdmi_tx <library/axi_hdmi_tx>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
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* - AXI_I2S_ADI
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- :git-hdl:`library/axi_i2s_adi <library/axi_i2s_adi>`
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- ---
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* - AXI_PWM_GEN
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- :git-hdl:`library/axi_pwm_gen`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_pwm_gen>`
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* - AXI_SPDIF_TX
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- :git-hdl:`library/axi_spdif_tx <library/axi_spdif_tx>`
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- ---
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* - AXI_SYSID
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- :git-hdl:`library/axi_sysid <library/axi_sysid>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - SYSID_ROM
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- :git-hdl:`library/sysid_rom <library/sysid_rom>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - UTIL_I2C_MIXER
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- :git-hdl:`library/util_i2c_mixer <library/util_i2c_mixer>`
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- ---
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.. include:: ../common/more_information.rst
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.. include:: ../common/support.rst
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