142 lines
2.8 KiB
Plaintext
142 lines
2.8 KiB
Plaintext
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TITLE
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Clock Generator (axi_clkgen)
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AXI_CLKGEN
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x0010
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REG_RSTN
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Interface Control & Status
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ENDREG
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FIELD
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[1] 0x0
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MMCM_RSTN
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RW
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MMCM reset (required for DRP access).
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Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
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ENDFIELD
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FIELD
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[0] 0x0
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RSTN
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RW
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Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0011
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REG_CLK_SEL
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Clock Select
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ENDREG
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FIELD
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[0] 0x0
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CLK_SEL
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RW
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Select betwen CLKIN1 (0x0) or CLKIN2 (0x1) input clock for the MMCM
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0017
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REG_MMCM_STATUS
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MMCM Status
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ENDREG
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FIELD
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[0] 0x0
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MMCM_LOCKED
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RO
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LOCKED status of the MMCM
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001c
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REG_DRP_CNTRL
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ADC Interface Control & Status
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ENDREG
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FIELD
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[28] 0x0
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DRP_RWN
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RW
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DRP read (0x1) or write (0x0) select (does not include GTX lanes).
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ENDFIELD
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FIELD
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[27:16] 0x000
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DRP_ADDRESS[11:0]
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RW
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DRP address, designs that contain more than one DRP accessible primitives
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have selects based on the most significant bits (does not include GTX lanes).
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ENDFIELD
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FIELD
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[15:0] 0x0000
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DRP_WDATA[15:0]
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RW
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DRP write data (does not include GTX lanes).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001d
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REG_DRP_STATUS
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MMCM Status
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ENDREG
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FIELD
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[17] 0x0
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MMCM_LOCKED
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RO
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LOCKED status of the MMCM
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ENDFIELD
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FIELD
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[16] 0x0
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DRP_STATUS
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RO
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If set indicates busy (access pending). The read data may not be valid if
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this bit is set (does not include GTX lanes).
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ENDFIELD
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FIELD
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[15:0] 0x0000
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DRP_RDATA
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RO
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DRP read data (does not include GTX lanes).
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ENDFIELD
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############################################################################################
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#############################################################################################
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REG
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0x0050
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REG_FPGA_VOLTAGE
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FPGA device voltage information
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ENDREG
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FIELD
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[15:0] 0x0
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FPGA_VOLTAGE
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RO
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The voltage of the FPGA device in mv
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ENDFIELD
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############################################################################################
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############################################################################################
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