2024-01-25 17:22:46 +00:00
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TITLE
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I3C Controller (i3c_controller_host_interface)
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i3c_controller_host_interface
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x00
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VERSION
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Version of the peripheral. Follows semantic versioning. Current version 0.01.00
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ENDREG
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FIELD
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[31:16] 0x00
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VERSION_MAJOR
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RO
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ENDFIELD
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FIELD
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[15:8] 0x01
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VERSION_MINOR
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RO
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ENDFIELD
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FIELD
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[7:0] 0x00
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VERSION_PATCH
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RO
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x01
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DEVICE_ID
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ENDREG
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FIELD
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[31:0] ''ID''
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DEVICE_ID
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RO
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Value of the ID configuration parameter.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x02
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SCRATCH
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ENDREG
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FIELD
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[31:0] 0x00000000
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SCRATCH
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RW
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Scratch register useful for debug.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x10
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ENABLE
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ENDREG
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FIELD
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[0] 0x1
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ENABLE
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RW
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Enable register. If the enable bit is set to 1 the internal state of the peripheral is reset.
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For proper operation, the bit needs to be set to 0.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x20
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IRQ_MASK
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ENDREG
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FIELD
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[7] 0x0
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DAA_PENDING
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RW
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If set to 0 the DAA_PENDING interrupt is masked.
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ENDFIELD
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FIELD
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[6] 0x0
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IBI_PENDING
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RW
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If set to 0 the IBI_PENDING interrupt is masked.
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ENDFIELD
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FIELD
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[5] 0x0
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CMDR_PENDING
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RW
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If set to 0 the CMDR_PENDING interrupt is masked.
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ENDFIELD
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FIELD
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[4] 0x0
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IBI_ALMOST_FULL
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RW
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If set to 0 the IBI_ALMOST_FULL interrupt is masked.
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ENDFIELD
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FIELD
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[3] 0x0
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SDI_ALMOST_FULL
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RW
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If set to 0 the SDI_ALMOST_FULL interrupt is masked.
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ENDFIELD
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FIELD
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[2] 0x0
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SDO_ALMOST_EMPTY
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RW
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If set to 0 the SDO_ALMOST_EMPTY interrupt is masked.
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ENDFIELD
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FIELD
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[1] 0x0
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CMDR_ALMOST_FULL
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RW
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If set to 0 the CMDR_ALMOST_FULL interrupt is masked.
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ENDFIELD
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FIELD
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[0] 0x0
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CMD_ALMOST_EMPTY
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RW
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If set to 0 the CMD_ALMOST_EMPTY interrupt is masked.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x21
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IRQ_PENDING
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ENDREG
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FIELD
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[31:0] 0x00000000
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IRQ_PENDING
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RW
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Pending IRQs with mask.
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Write 1 at the CMDR_PENDING bit to clear it.
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For CMDR_PENDING and IBI_PENDING, will be cleared if the FIFOs are also empty.
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For DAA_PENDING, will be cleared if the SDO FIFO is not empty, that means, got dynamic
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address in the pipeline.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x22
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IRQ_SOURCE
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ENDREG
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FIELD
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[31:0] 0x00000000
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IRQ_SOURCE
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RO
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Pending IRQs without mask.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x30
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CMD_FIFO_ROOM
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ENDREG
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FIELD
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[31:0] 0xXXXXXXXX
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CMD_FIFO_ROOM
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RO
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Number of free entries in the CMD FIFO.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x31
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CMDR_FIFO_LEVEL
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ENDREG
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FIELD
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[31:0] 0x00000000
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CMDR_FIFO_LEVEL
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RO
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Number of valid entries in the CMDR FIFO.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x32
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SDO_FIFO_ROOM
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ENDREG
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FIELD
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[31:0] 0xXXXXXXXX
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SDO_FIFO_ROOM
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RO
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Number of free entries in the SDO FIFO.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x33
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SDI_FIFO_LEVEL
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ENDREG
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FIELD
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[31:0] 0x00000000
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SDI_FIFO_LEVEL
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RO
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Number of valid entries in the serial-data-in FIFO.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x34
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IBI_FIFO_LEVEL
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ENDREG
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FIELD
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[31:0] 0x00000000
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IBI_FIFO_LEVEL
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RO
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Number of valid entries in the in-bus-interrupt FIFO.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x35
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CMD_FIFO
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Command FIFO register. Writing to this register inserts an entry into the CMD FIFO.
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Writing to this register when the CMD FIFO is full has no effect and the written entry
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is discarded. Reading from this register always returns 0x00000000.
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The Software is responsive for a valid sequence of commands.
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If the peripheral does not ACK when required during a command, the procedure exits and the
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next command in the FIFO is interpreted.
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See :ref:`i3c_controller instruction-format` for the structure of the command.
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ENDREG
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FIELD
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[22] 0xX
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CMD_IS_CCC
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WO
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Indicate if it is a CCC transfer (1) or not (0).
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ENDFIELD
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FIELD
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[21] 0xX
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CMD_BCAST_HEADER
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WO
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Include broadcast header in private transfer (1) or not (0).
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ENDFIELD
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FIELD
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[20] 0xX
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CMD_SR
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WO
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Repeated start flag, yield a Sr (1) or P (0) at the end of the transfer.
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ENDFIELD
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FIELD
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[19:8] 0xXXX
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CMD_BUFFER_LENGHT
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WO
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Unsigned 12-bits payload length, direction depends on RNW value.
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ENDFIELD
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FIELD
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[7:1] 0xXX
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CMD_DA
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WO
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7-bit device address (don’t care in broadcast mode).
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ENDFIELD
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FIELD
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[0] 0xX
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CMD_RNW
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WO
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If should retrieve data from device (1) or not (0).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x36
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CMDR_FIFO
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CMDR FIFO register. Reading from this register removes the first entry from the CMDR FIFO.
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Reading this register when the CMDR FIFO is empty will return undefined data.
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Writing to it has no effect.
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ENDREG
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FIELD
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[23:0] 0x??
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CMDR_FIFO_ERROR
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RO
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If an error occurred during the transfer.
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ENDFIELD
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FIELD
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[19:8] 0x??
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CMDR_FIFO_BUFFER_LENGTH
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RO
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Unsigned 12-bits transferred payload length.
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ENDFIELD
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FIELD
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[7:0] 0x??
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CMDR_FIFO_SYNC
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RO
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Command synchronization.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x37
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SDO_FIFO
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SDO FIFO register. Writing to this register inserts an entry into the SDO FIFO.
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Writing to this register when the SDO FIFO is full has no effect and the written entry
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is discarded. Reading from this register always returns 0x00000000.
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ENDREG
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FIELD
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[31:24] 0xXX
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SDO_FIFO_BYTE_3
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RO
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ENDFIELD
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FIELD
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[23:16] 0xXX
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SDO_FIFO_BYTE_2
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RO
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ENDFIELD
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FIELD
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[15:8] 0xXX
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SDO_FIFO_BYTE_1
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RO
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ENDFIELD
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FIELD
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[7:0] 0xXX
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SDO_FIFO_BYTE_0
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RO
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x38
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SDI_FIFO
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SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO.
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Reading this register when the SDI FIFO is empty will return undefined data.
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Writing to it has no effect.
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ENDREG
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FIELD
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[31:0] 0xXXXXXXXX
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SDI_FIFO
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RO
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x39
|
|
|
|
|
IBI_FIFO
|
|
|
|
|
IBI FIFO register. Reading from this register removes the first entry from the IBI FIFO.
|
|
|
|
|
Reading this register when the IBI FIFO is empty will return undefined data.
|
|
|
|
|
Writing to it has no effect.
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[23:17] 0xXX
|
|
|
|
|
IBI_FIFO_DA
|
|
|
|
|
RO
|
|
|
|
|
IBI Dynamic address.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[15:8] 0xXX
|
|
|
|
|
IBI_FIFO_MDB
|
|
|
|
|
RO
|
|
|
|
|
IBI MDB, if the peripheral's BCR[2] is Low, the field is ignored.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[7:0] 0xXX
|
|
|
|
|
IBI_FIFO_SYNC
|
|
|
|
|
RO
|
|
|
|
|
Synchronization number.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x3a
|
|
|
|
|
FIFO_STATUS
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[2] 0x1
|
|
|
|
|
SDI_EMPTY
|
|
|
|
|
RO
|
|
|
|
|
If there is no element to be read in the SDI FIFO.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[1] 0x1
|
|
|
|
|
IBI_EMPTY
|
|
|
|
|
RO
|
|
|
|
|
If there is no element to be read in the IBI FIFO.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[0] 0x1
|
|
|
|
|
CMDR_EMPTY
|
|
|
|
|
RO
|
|
|
|
|
If there is no element to be read in the CMDR FIFO.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x40
|
|
|
|
|
OPS
|
|
|
|
|
Configure the operation of the controller.
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[7] 0x0
|
|
|
|
|
OPS_STATUS_NOP
|
|
|
|
|
RO
|
|
|
|
|
This bit is set to 1 when the bus is not executing any procedure.
|
|
|
|
|
It is not idle bus condition since it set right after the Stop.
|
2024-04-30 15:14:47 +00:00
|
|
|
|
ENDFIELD
|
2024-01-25 17:22:46 +00:00
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[6:5] 0x0
|
|
|
|
|
OPS_SPEED_GRADE
|
|
|
|
|
RW
|
|
|
|
|
Sets the speed grade in push-pull mode.
|
|
|
|
|
Speed with 100MHz driver clock are:
|
|
|
|
|
00: 1.56MHz (default)
|
|
|
|
|
01: 3.12MHz
|
|
|
|
|
10: 6.25MHz
|
|
|
|
|
11: 12.50MHz
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[4:1] 0x0
|
|
|
|
|
OPS_OFFLOAD_LENGTH
|
|
|
|
|
RW
|
|
|
|
|
Offload commands length.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[0] 0x0
|
|
|
|
|
OPS_MODE
|
|
|
|
|
RW
|
|
|
|
|
Set 0 to direct transfers, 1 to offload operation.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x50
|
|
|
|
|
IBI_CONFIG
|
|
|
|
|
Configure the In-Band Interrupt (IBI) feature.
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[1] 0x0
|
2024-04-30 15:14:47 +00:00
|
|
|
|
IBI_CONFIG_LISTEN
|
2024-01-25 17:22:46 +00:00
|
|
|
|
WO
|
2024-04-30 15:14:47 +00:00
|
|
|
|
Set this bit to listen for IBI requests (when a peripheral pulls SDA Low during bus available).
|
2024-01-25 17:22:46 +00:00
|
|
|
|
After the IBI request is resolved, the controller returns to idle, since it is was not doing
|
|
|
|
|
a cmd transfer.
|
2024-04-30 15:14:47 +00:00
|
|
|
|
This should be set to 1 during normal operation, even if IBI_CONFIG_ENABLE is disabled.
|
2024-01-25 17:22:46 +00:00
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[0] 0x0
|
|
|
|
|
IBI_CONFIG_ENABLE
|
|
|
|
|
WO
|
|
|
|
|
Set this bit to accept (ACK) IBI requests.
|
|
|
|
|
If disabled, the controller will NACK IBI requests.
|
|
|
|
|
If enabled, the controller will ACK the IBI request and receive the MDB.
|
|
|
|
|
In both cases, the controller will proceed with the cmd transfer after resolving the IBI
|
2024-04-30 15:14:47 +00:00
|
|
|
|
request, if any.
|
|
|
|
|
Accepted IBIs fill the IBI_FIFO and generate an interrupt to the PS.
|
|
|
|
|
IBI_CONFIG_LISTEN set to 1 and IBI_CONFIG_ENABLE set to 0 ensures that incoming IBIs are
|
|
|
|
|
rejected as they come.
|
2024-01-25 17:22:46 +00:00
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x60
|
|
|
|
|
DEV_CHAR
|
|
|
|
|
Holds devices characteristics that are looked-up during execution.
|
|
|
|
|
The content is written only by software.
|
|
|
|
|
To read an address, write the address with DEV_CHAR_0_WEN 0 and then read.
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[15:9] 0x00
|
|
|
|
|
DEV_CHAR_ADDR
|
|
|
|
|
RW
|
|
|
|
|
Device address to apply DEV_CHAR[3:0].
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[8] 0xX
|
|
|
|
|
DEV_CHAR_WEN
|
|
|
|
|
W
|
|
|
|
|
Enable write of the fields.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[3] 0x0
|
2024-04-30 15:14:47 +00:00
|
|
|
|
DEV_CHAR_HAS_IBI_PAYLOAD
|
2024-01-25 17:22:46 +00:00
|
|
|
|
RW
|
2024-04-30 15:14:47 +00:00
|
|
|
|
Indicates if the device sends at least MDB during the IBI.
|
2024-01-25 17:22:46 +00:00
|
|
|
|
0 does not, 1 does.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[2] 0x0
|
|
|
|
|
DEV_CHAR_IS_IBI_CAPABLE
|
|
|
|
|
RW
|
|
|
|
|
Indicates if the device can send IBI.
|
|
|
|
|
0 does not, 1 does.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[1] 0x0
|
|
|
|
|
DEV_CHAR_IS_ATTACHED
|
|
|
|
|
RW
|
|
|
|
|
Indicate if the device is attached.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
[0] 0x0
|
|
|
|
|
DEV_CHAR_IS_I2C
|
|
|
|
|
RW
|
|
|
|
|
Indicates if the device is I²C.
|
|
|
|
|
0 is I3C device, 1 is I²C device.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0xb0 + 0x01*n
|
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
|
|
|
|
WHERE n IS FROM 0 TO 15
|
2024-01-25 17:22:46 +00:00
|
|
|
|
OFFLOAD_CMD_n
|
|
|
|
|
Offload command memory. Write commands in sequence to these addresses and update the
|
|
|
|
|
OFFLOAD_CMD_LENGTH register.
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[31:0] 0x00
|
|
|
|
|
OFFLOAD_CMD
|
|
|
|
|
RW
|
|
|
|
|
The command to the I3C controller to execute.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0xc0 + 0x01*n
|
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
|
|
|
|
WHERE n IS FROM 0 TO 15
|
2024-01-25 17:22:46 +00:00
|
|
|
|
OFFLOAD_SDO_n
|
|
|
|
|
Offload SDO memory.
|
|
|
|
|
Dual access memory sector used to store the SDO payload for the offload execution.
|
|
|
|
|
The SDO is read by the parsing the OFFLOAD_CMD commands.
|
|
|
|
|
For example, if the first command on OFFLOAD_CMD is a write with length 3 and the next with
|
|
|
|
|
length 2, 3 bytes from OFFLOAD_SDO_0 are sent, then 2 bytes from OFFLOAD_SDO_1 are sent.
|
|
|
|
|
If OPS_OFFLOAD_LENGTH is 2, then the burst concludes and the "pointer" resets to
|
|
|
|
|
OFFLOAD_SDO_0, otherwise, the execution continues until all commands are resolved, always
|
|
|
|
|
bounded by OPS_OFFLOAD_LENGTH.
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[31:24] 0x00
|
|
|
|
|
OFFLOAD_SDO_BYTE_3
|
|
|
|
|
RO
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[23:16] 0x00
|
|
|
|
|
OFFLOAD_SDO_BYTE_2
|
|
|
|
|
RO
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[15:8] 0x00
|
|
|
|
|
OFFLOAD_SDO_BYTE_1
|
|
|
|
|
RO
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[7:0] 0x00
|
|
|
|
|
OFFLOAD_SDO_BYTE_0
|
|
|
|
|
RO
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|