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.. _user_guide:
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User Guide
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===============================================================================
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.. toctree::
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:hidden:
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2023-07-20 13:04:46 +00:00
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Introduction <introduction>
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Git repository <git_repository>
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Releases <releases>
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Build an HDL project <build_hdl>
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HDL architecture <architecture>
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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IP cores <ip_cores/index>
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Porting reference designs <porting_project>
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Customize HDL projects <customize_hdl>
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HDL coding guideline <hdl_coding_guideline>
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2023-09-06 18:38:30 +00:00
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Documentation guidelines <docs_guidelines>
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2023-07-20 13:04:46 +00:00
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Third party forks <third_party>
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2023-09-06 18:38:30 +00:00
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2023-07-20 13:04:46 +00:00
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`Analog Devices, Inc.`_ provides FPGA reference designs for selected hardware
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featuring some of our products interfacing to publicly available FPGA
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evaluation boards.
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This wiki documentation explains the HDL resources of these reference designs.
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Contents
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-------------------------------------------------------------------------------
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#. :ref:`introduction`
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#. :ref:`git_repository`: Our HDL GitHub repository
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#. :ref:`releases`: Releases and supported tool versions
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#. :ref:`build_hdl`: Building and generating the programming files
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#. :ref:`architecture`: HDL project architecture explained
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docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 13:05:12 +00:00
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#. :ref:`user_guide ip_cores`: List of IP cores and IP guides.
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2023-09-06 18:38:30 +00:00
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#. :ref:`porting_project`: How to port a project to a non-supported carrier
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2023-07-20 13:04:46 +00:00
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#. :ref:`customize_hdl`: Using and modifying the HDL design
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#. :ref:`hdl_coding_guideline`: The Verilog/VHDL coding guidelines that the
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2024-02-22 14:32:04 +00:00
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HDL team follows
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#. :ref:`docs_guidelines`: Documentation guidelines
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#. :ref:`third_party`: Third party forks with derived work
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#. :dokuwiki:`Reference designs using AMD Xilinx hardware <resources/alliances/xilinx>`
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#. :dokuwiki:`Reference designs using Intel hardware <resources/alliances/altera>`
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2023-07-20 13:04:46 +00:00
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.. _Analog Devices, Inc.: https://www.analog.com/en/index.html
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