pluto_hdl_adi/library/xilinx/util_clkdiv/util_clkdiv.v

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// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
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// The user should read each of these license terms, and understand the
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module util_clkdiv (
  input   clk,
  input   clk_sel,
  output  clk_out
);

  parameter SIM_DEVICE = "7SERIES";
  parameter SEL_0_DIV = "4";
  parameter SEL_1_DIV = "2";

  wire clk_div_sel_0_s;
  wire clk_div_sel_1_s;

  generate if (SIM_DEVICE == "7SERIES") begin

    BUFR #(
      .BUFR_DIVIDE(SEL_0_DIV),
      .SIM_DEVICE("7SERIES")
    ) clk_divide_sel_0 (
      .I(clk),
      .CE(1),
      .CLR(0),
      .O(clk_div_sel_0_s));

    BUFR #(
      .BUFR_DIVIDE(SEL_1_DIV),
      .SIM_DEVICE("7SERIES")
    ) clk_divide_sel_1 (
      .I(clk),
      .CE(1),
      .CLR(0),
      .O(clk_div_sel_1_s));

  end else if (SIM_DEVICE == "ULTRASCALE") begin

    BUFGCE_DIV #(
      .BUFGCE_DIVIDE(SEL_0_DIV)
    ) clk_divide_sel_0 (
      .I(clk),
      .CE(1),
      .CLR(0),
      .O(clk_div_sel_0_s));

    BUFGCE_DIV #(
      .BUFGCE_DIVIDE(SEL_1_DIV)
    ) clk_divide_sel_1 (
      .I(clk),
      .CE(1),
      .CLR(0),
      .O(clk_div_sel_1_s));

  end endgenerate

  BUFGMUX_CTRL i_div_clk_gbuf (
    .I0(clk_div_sel_0_s), // 1-bit input: Clock input (S=0)
    .I1(clk_div_sel_1_s), // 1-bit input: Clock input (S=1)
    .S(clk_sel),
    .O (clk_out));

endmodule