2022-09-21 12:12:35 +00:00
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TITLE
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DMA Controller (axi_dmac)
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DMAC
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x000
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VERSION
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2022-10-18 13:21:34 +00:00
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Version of the peripheral. Follows semantic versioning. Current version 4.04.61.
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2022-09-21 12:12:35 +00:00
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ENDREG
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FIELD
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[31:16] 0x04
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VERSION_MAJOR
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RO
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ENDFIELD
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FIELD
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[15:8] 0x03
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VERSION_MINOR
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RO
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ENDFIELD
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FIELD
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[7:0] 0x61
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VERSION_PATCH
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RO
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x001
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PERIPHERAL_ID
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ENDREG
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FIELD
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[31:0] ''ID''
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PERIPHERAL_ID
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RO
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Value of the ID configuration parameter.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x002
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SCRATCH
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ENDREG
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FIELD
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[31:0] 0x00000000
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SCRATCH
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RW
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Scratch register useful for debug.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x003
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IDENTIFICATION
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ENDREG
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FIELD
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[31:0] 0x444D4143
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IDENTIFICATION
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RO
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Peripheral identification ('D', 'M', 'A', 'C').
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x004
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INTERFACE_DESCRIPTION
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ENDREG
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FIELD
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[3:0] log2(''DMA_DATA_WIDTH_DEST''/8)
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BYTES_PER_BEAT_DEST_LOG2
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R
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Width of data bus on destination interface. Log2 of interface data widths in bytes.
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ENDFIELD
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FIELD
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[5:4] ''DMA_TYPE_DEST''
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DMA_TYPE_DEST
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R
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Value of ''DMA_TYPE_DEST'' parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO )
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ENDFIELD
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FIELD
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[11:8] log2(''DMA_DATA_WIDTH_SRC''/8)
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BYTES_PER_BEAT_SRC_LOG2
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R
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Width of data bus on source interface. Log2 of interface data widths in bytes.
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ENDFIELD
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FIELD
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[13:12] ''DMA_TYPE_SRC''
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DMA_TYPE_SRC
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R
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Value of ''DMA_TYPE_SRC'' parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO )
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ENDFIELD
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FIELD
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[19:16] ''BYTES_PER_BURST_WIDTH''
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BYTES_PER_BURST_WIDTH
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R
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Value of ''BYTES_PER_BURST_WIDTH'' interface parameter. Log2 of the real ''MAX_BYTES_PER_BURST''.
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The starting address of the transfer must be aligned with ''MAX_BYTES_PER_BURST'' to avoid crossing
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the 4kB address boundary.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x020
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IRQ_MASK
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ENDREG
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FIELD
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[1] 0x1
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TRANSFER_COMPLETED
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RW
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Masks the TRANSFER_COMPLETED IRQ.
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ENDFIELD
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FIELD
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[0] 0x1
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TRANSFER_QUEUED
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RW
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Masks the TRANSFER_QUEUED IRQ.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x021
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IRQ_PENDING
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ENDREG
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FIELD
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[1] 0x0
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TRANSFER_COMPLETED
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RW1C
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This bit will be asserted if a transfer has been completed and the
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TRANSFER_COMPLETED bit in the IRQ_MASK register is not set. Either if all bytes have been
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transferred or an error occurred during the transfer.
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ENDFIELD
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FIELD
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[0] 0x0
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TRANSFER_QUEUED
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RW1C
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This bit will be asserted if a transfer has been queued and it is possible to queue
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the next transfer. It can be masked out by setting the TRANSFER_QUEUED bit in the
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IRQ_MASK register.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x022
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IRQ_SOURCE
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ENDREG
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FIELD
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[1] 0x0
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TRANSFER_COMPLETED
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RO
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This bit will be asserted if a transfer has been completed. Either if all bytes have been
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transferred or an error occurred during the transfer. Cleared together with the corresponding IRQ_PENDING bit.
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ENDFIELD
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FIELD
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[0] 0x0
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TRANSFER_QUEUED
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RO
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This bit will be asserted if a transfer has been queued and it is possible to queue
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the next transfer. Cleared together with the corresponding IRQ_PENDING bit.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x100
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CONTROL
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ENDREG
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FIELD
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[1] 0x0
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PAUSE
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RW
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When set to 1 the currently active transfer is paused. It will be resumed once the bit is
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cleared again.
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ENDFIELD
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FIELD
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[0] 0x0
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ENABLE
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RW
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When set to 1 the DMA channel is enabled.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x101
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TRANSFER_ID
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ENDREG
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FIELD
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[1:0] 0x00
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TRANSFER_ID
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RO
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This register contains the ID of the next transfer. The ID is generated by the DMAC and after the
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transfer has been started can be used to check if the transfer has finished by checking the
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corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if
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TRANSFER_SUBMIT is 0.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x102
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TRANSFER_SUBMIT
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ENDREG
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FIELD
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[0] 0x00
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TRANSFER_SUBMIT
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RW
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Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once
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the transfer has been queued or the DMA channel is disabled.
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Writing a 0 to this register has no effect.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x103
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FLAGS
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ENDREG
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FIELD
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[0] ''CYCLIC''
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CYCLIC
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RW
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Setting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode
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the controller will re-start a transfer again once it has finished. In cyclic
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mode no end-of-transfer interrupts will be generated.
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ENDFIELD
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FIELD
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[1] 0x1
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TLAST
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RW
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When setting this bit for a MM to AXIS transfer the TLAST signal
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will be asserted during the last beat of the transfer.
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For AXIS to MM transfers the TLAST signal from the AXIS interface is monitored.
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After its occurrence all descriptors are ignored until this bit is set.
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ENDFIELD
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FIELD
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[2] 0x0
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PARTIAL_REPORTING_EN
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RW
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When setting this bit the length of partial transfers caused eventually by TLAST will be recorded.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x104
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DEST_ADDRESS
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ENDREG
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FIELD
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[31:0] 0x00000000
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DEST_ADDRESS
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RW
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This register contains the destination address of the transfer. The address needs to be aligned
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to the bus width.
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This register is only valid if the DMA channel has been configured for write to memory support.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x105
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SRC_ADDRESS
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ENDREG
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FIELD
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[31:0] 0x00000000
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SRC_ADDRESS
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RW
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This register contains the source address of the transfer. The address needs to be aligned
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to the bus width.
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This register is only valid if the DMA channel has been configured for read from memory support.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x106
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X_LENGTH
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ENDREG
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FIELD
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docs: links, drop part, fixups, codeowners
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-11-13 15:42:46 +00:00
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[23:0] {log2(max(''DMA_DATA_WIDTH_SRC'', ''DMA_DATA_WIDTH_DEST'')/8){1'b1}}
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2022-09-21 12:12:35 +00:00
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X_LENGTH
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RW
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Number of bytes to transfer - 1.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x107
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Y_LENGTH
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ENDREG
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FIELD
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[23:0] 0x000000
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Y_LENGTH
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RW
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Number of rows to transfer - 1.
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Note, this field is only valid if the DMA channel has been configured with 2D transfer support.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x108
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DEST_STRIDE
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ENDREG
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FIELD
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[23:0] 0x000000
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DEST_STRIDE
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RW
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The number of bytes between the start of one row and the next row for the
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destination address. Needs to be aligned to the bus width.
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|
|
|
|
|
|
|
|
Note, this field is only valid if the DMA channel has been configured with 2D
|
|
|
|
|
transfer support and write to memory support.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x109
|
|
|
|
|
SRC_STRIDE
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[23:0] 0x000000
|
|
|
|
|
SRC_STRIDE
|
|
|
|
|
RW
|
|
|
|
|
The number of bytes between the start of one row and the next row for the source
|
|
|
|
|
address. Needs to be aligned to the bus width.
|
|
|
|
|
|
|
|
|
|
Note, this field is only valid if the DMA channel has been configured with 2D
|
|
|
|
|
transfer and read from memory support.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x10a
|
|
|
|
|
TRANSFER_DONE
|
|
|
|
|
If bit x is set in this register the transfer with ID x has been completed. The bit will automatically
|
|
|
|
|
be cleared when a new transfer with this ID is queued and will be set when the transfer has been completed.
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[0] 0x0
|
|
|
|
|
TRANSFER_0_DONE
|
|
|
|
|
RO
|
|
|
|
|
If this bit is set the transfer with ID 0 has been completed.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[1] 0x0
|
|
|
|
|
TRANSFER_1_DONE
|
|
|
|
|
RO
|
|
|
|
|
If this bit is set the transfer with ID 1 has been completed.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[2] 0x0
|
|
|
|
|
TRANSFER_2_DONE
|
|
|
|
|
RO
|
|
|
|
|
If this bit is set the transfer with ID 2 has been completed.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[3] 0x0
|
|
|
|
|
TRANSFER_3_DONE
|
|
|
|
|
RO
|
|
|
|
|
If this bit is set the transfer with ID 3 has been completed.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[31] 0x0
|
|
|
|
|
PARTIAL_TRANSFER_DONE
|
|
|
|
|
RO
|
|
|
|
|
If this bit is set at least one partial transfer was transferred.
|
|
|
|
|
This field will reset when the ENABLE control bit is reset or when
|
|
|
|
|
all information on partial transfers was read through PARTIAL_TRANSFER_LENGTH and
|
|
|
|
|
PARTIAL_TRANSFER_ID registers.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x10b
|
|
|
|
|
ACTIVE_TRANSFER_ID
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[4:0] 0x00
|
|
|
|
|
ACTIVE_TRANSFER_ID
|
|
|
|
|
RO
|
|
|
|
|
ID of the currently active transfer. When no transfer is active this register will be equal to
|
|
|
|
|
the TRANSFER_ID register.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x10c
|
|
|
|
|
STATUS
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[31:0] 0x00
|
|
|
|
|
RESERVED
|
|
|
|
|
RO
|
|
|
|
|
This register is reserved for future usage. Reading it will always return 0.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x10d
|
|
|
|
|
CURRENT_DEST_ADDRESS
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[31:0] 0x00
|
|
|
|
|
CURRENT_DEST_ADDRESS
|
|
|
|
|
RO
|
|
|
|
|
Address to which the next data sample is written to.
|
|
|
|
|
|
|
|
|
|
This register is only valid if the DMA channel has been configured for write to memory support.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x10e
|
|
|
|
|
CURRENT_SRC_ADDRESS
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[31:0] 0x00
|
|
|
|
|
CURRENT_SRC_ADDRESS
|
|
|
|
|
RO
|
|
|
|
|
Address form which the next data sample is read.
|
|
|
|
|
|
|
|
|
|
This register is only valid if the DMA channel has been configured for read from memory support.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x112
|
|
|
|
|
TRANSFER_PROGRESS
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[23:0] 0x000000
|
|
|
|
|
TRANSFER_PROGRESS
|
|
|
|
|
RO
|
|
|
|
|
This field presents the number of bytes transferred to the destination for the current transfer.
|
|
|
|
|
This register will be cleared once the transfer completes.
|
|
|
|
|
This should be used for debugging purposes only.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x113
|
|
|
|
|
PARTIAL_TRANSFER_LENGTH
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[31:0] 0x000000
|
|
|
|
|
PARTIAL_LENGTH
|
|
|
|
|
RO
|
|
|
|
|
Length of the partial transfer in bytes. Represents the number of bytes received
|
|
|
|
|
until the moment of TLAST assertion. This will be smaller than the programmed length
|
|
|
|
|
from the X_LENGTH and Y_LENGTH registers.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x114
|
|
|
|
|
PARTIAL_TRANSFER_ID
|
|
|
|
|
Must be read after the PARTIAL_TRANSFER_LENGTH registers.
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[1:0] 0x0
|
|
|
|
|
PARTIAL_TRANSFER_ID
|
|
|
|
|
RO
|
|
|
|
|
ID of the transfer that was partial.
|
|
|
|
|
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
2022-10-18 13:21:34 +00:00
|
|
|
REG
|
|
|
|
|
0x124
|
|
|
|
|
DEST_ADDRESS_HIGH
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[31:0] 0x00000000
|
|
|
|
|
DEST_ADDRESS_HIGH
|
|
|
|
|
RW
|
|
|
|
|
This register contains the HIGH segment of the destination address of the transfer.
|
|
|
|
|
|
|
|
|
|
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if DMA channel has been configured for write to memory support.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x125
|
|
|
|
|
SRC_ADDRESS_HIGH
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[31:0] 0x00000000
|
|
|
|
|
SRC_ADDRESS_HIGH
|
|
|
|
|
RW
|
|
|
|
|
This register contains the HIGH segment of the source address of the transfer.
|
|
|
|
|
|
|
|
|
|
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
2022-09-21 12:12:35 +00:00
|
|
|
|
2022-10-18 13:21:34 +00:00
|
|
|
REG
|
|
|
|
|
0x126
|
|
|
|
|
CURRENT_DEST_ADDRESS_HIGH
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[31:0] 0x00
|
|
|
|
|
CURRENT_DEST_ADDRESS_HIGH
|
|
|
|
|
RO
|
|
|
|
|
HIGH segment of the address to which the next data sample is written to.
|
|
|
|
|
|
|
|
|
|
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for write to memory support.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
REG
|
|
|
|
|
0x127
|
|
|
|
|
CURRENT_SRC_ADDRESS_HIGH
|
|
|
|
|
ENDREG
|
|
|
|
|
|
|
|
|
|
FIELD
|
|
|
|
|
[31:0] 0x00
|
|
|
|
|
CURRENT_SRC_ADDRESS_HIGH
|
|
|
|
|
RO
|
|
|
|
|
HIGH segment of the address from which the next data sample is read.
|
|
|
|
|
|
|
|
|
|
This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
|
|
|
|
|
ENDFIELD
|
|
|
|
|
|
|
|
|
|
############################################################################################
|
|
|
|
|
############################################################################################
|
