pluto_hdl_adi/library/common/ad_ss_422to444.v

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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Input must be RGB or CrYCb in that order, output is CrY/CbY
`timescale 1ns/100ps
module ad_ss_422to444 #(
parameter CR_CB_N = 0,
parameter DELAY_DATA_WIDTH = 16
) (
// 422 inputs
input clk,
input s422_de,
input [DELAY_DATA_WIDTH-1:0] s422_sync,
input [ 15:0] s422_data,
// 444 outputs
output reg [DELAY_DATA_WIDTH-1:0] s444_sync,
output reg [ 23:0] s444_data
);
localparam DW = DELAY_DATA_WIDTH - 1;
// internal registers
reg cr_cb_sel = 'd0;
reg s422_de_d = 'd0;
reg [DW:0] s422_sync_d = 'd0;
reg s422_de_2d = 'd0;
reg [7:0] s422_Y_d;
reg [7:0] s422_CbCr_d;
reg [7:0] s422_CbCr_2d;
reg [ 8:0] s422_CbCr_avg;
// internal wires
wire [ 7:0] s422_Y;
wire [ 7:0] s422_CbCr;
// Input format is
// [15:8] Cb/Cr
// [ 7:0] Y
//
// Output format is
// [23:15] Cr
// [16: 8] Y
// [ 7: 0] Cb
assign s422_Y = s422_data[7:0];
assign s422_CbCr = s422_data[15:8];
// first data on de assertion is cb (0x0), then cr (0x1).
// previous data is held when not current
always @(posedge clk) begin
if (s422_de_d == 1'b1) begin
cr_cb_sel <= ~cr_cb_sel;
end else begin
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
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cr_cb_sel <= CR_CB_N;
end
end
// pipe line stages
always @(posedge clk) begin
s422_de_d <= s422_de;
s422_sync_d <= s422_sync;
s422_de_2d <= s422_de_d;
s422_Y_d <= s422_Y;
s422_CbCr_d <= s422_CbCr;
s422_CbCr_2d <= s422_CbCr_d;
end
// If both the left and the right sample are valid do the average, otherwise
// use the only valid.
always @(s422_de_2d, s422_de, s422_CbCr, s422_CbCr_2d)
begin
if (s422_de == 1'b1 && s422_de_2d)
s422_CbCr_avg <= s422_CbCr + s422_CbCr_2d;
else if (s422_de == 1'b1)
s422_CbCr_avg <= {s422_CbCr, 1'b0};
else
s422_CbCr_avg <= {s422_CbCr_2d, 1'b0};
end
// 444 outputs
always @(posedge clk) begin
s444_sync <= s422_sync_d;
s444_data[15:8] <= s422_Y_d;
if (cr_cb_sel) begin
s444_data[23:16] <= s422_CbCr_d;
s444_data[ 7: 0] <= s422_CbCr_avg[8:1];
end else begin
s444_data[23:16] <= s422_CbCr_avg[8:1];
s444_data[ 7: 0] <= s422_CbCr_d;
end
end
endmodule