28 lines
1.2 KiB
Plaintext
28 lines
1.2 KiB
Plaintext
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# Primary clock definitions
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# These two reference clocks are connect to the same source on the PCB
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create_clock -name refclk -period 4.00 [get_ports fpga_clk_m2c_p[0]]
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create_clock -name refclk_replica -period 4.00 [get_ports fpga_clk_m2c_0_replica_n]
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# rx device clock
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create_clock -name rx_device_clk -period 4.00 [get_ports fpga_clk_m2c_p[1]]
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# tx device clock
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create_clock -name tx_device_clk -period 4.00 [get_ports fpga_clk_m2c_p[2]]
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# SPI 2 clock
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create_generated_clock -name spi_2_clk \
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-source [get_pins i_system_wrapper/system_i/axi_spi_2/ext_spi_clk] \
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-divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi_2/sck_o]
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# Constraint SYSREFs
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# Assumption is that REFCLK and SYSREF have similar propagation delay,
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# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
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set_input_delay -clock [get_clocks rx_device_clk] \
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[get_property PERIOD [get_clocks rx_device_clk]] \
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[get_ports {fpga_sysref_m2c_*}]
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set_input_delay -clock [get_clocks tx_device_clk] -add_delay\
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[get_property PERIOD [get_clocks tx_device_clk]] \
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[get_ports {fpga_sysref_m2c_*}]
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set_clock_groups -group rx_device_clk -group tx_device_clk -asynchronous
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