2018-08-10 07:34:45 +00:00
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## FIFO depth is 1GB, PL_DDR is used
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2017-02-27 21:05:21 +00:00
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set adc_fifo_address_width 16
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2018-08-10 07:34:45 +00:00
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## FIFO depth is 8Mb - 500k samples
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set dac_fifo_address_width 16
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2017-02-27 21:05:21 +00:00
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2018-08-10 07:34:45 +00:00
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## NOTE: With this configuration the #36Kb BRAM utilization is at ~47%
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2015-06-26 09:04:19 +00:00
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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2017-02-22 20:56:37 +00:00
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source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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2015-06-26 09:04:19 +00:00
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source ../common/daq3_bd.tcl
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2020-10-09 14:28:10 +00:00
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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2015-06-26 09:04:19 +00:00
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2022-09-23 09:28:22 +00:00
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set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
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2019-06-28 08:41:21 +00:00
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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2022-09-23 09:28:22 +00:00
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
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2019-06-28 08:41:21 +00:00
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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2020-09-28 21:10:35 +00:00
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sysid_gen_sys_init_file
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