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pluto_hdl_adi/library/common/up_tdd_cntrl.v

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axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_tdd_cntrl (
clk,
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
rst,
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
//rf tdd interface control
tdd_enable,
tdd_secondary,
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
tdd_rx_only,
tdd_tx_only,
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
tdd_gated_rx_dmapath,
tdd_gated_tx_dmapath,
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
tdd_burst_count,
tdd_counter_init,
tdd_frame_length,
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
tdd_terminal_type,
fmcomms2/TDD: Update synchronization interface Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 12:14:36 +00:00
tdd_sync_enable,
axi_ad9361/tdd: Update the synchronization logic The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 09:21:23 +00:00
tdd_sync_period,
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2,
tdd_status,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00010001;
hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N
2015-08-19 11:11:47 +00:00
parameter ID = 0;
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
input clk;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
input rst;
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
output tdd_enable;
output tdd_secondary;
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
output tdd_rx_only;
output tdd_tx_only;
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
output tdd_gated_rx_dmapath;
output tdd_gated_tx_dmapath;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
output [ 7:0] tdd_burst_count;
output [23:0] tdd_counter_init;
output [23:0] tdd_frame_length;
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
output tdd_terminal_type;
fmcomms2/TDD: Update synchronization interface Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 12:14:36 +00:00
output tdd_sync_enable;
ad_tdd_sync: Update the synchronization logic The synchronization interface is a single bidirectional line. Output for Master, input for Slave. The sync_period value is relative to frame length and the digital interface clock. The actual synchronization period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 09:31:58 +00:00
output [ 7:0] tdd_sync_period;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
output [23:0] tdd_vco_rx_on_1;
output [23:0] tdd_vco_rx_off_1;
output [23:0] tdd_vco_tx_on_1;
output [23:0] tdd_vco_tx_off_1;
output [23:0] tdd_rx_on_1;
output [23:0] tdd_rx_off_1;
output [23:0] tdd_tx_on_1;
output [23:0] tdd_tx_off_1;
output [23:0] tdd_tx_dp_on_1;
output [23:0] tdd_tx_dp_off_1;
output [23:0] tdd_vco_rx_on_2;
output [23:0] tdd_vco_rx_off_2;
output [23:0] tdd_vco_tx_on_2;
output [23:0] tdd_vco_tx_off_2;
output [23:0] tdd_rx_on_2;
output [23:0] tdd_rx_off_2;
output [23:0] tdd_tx_on_2;
output [23:0] tdd_tx_off_2;
output [23:0] tdd_tx_dp_on_2;
output [23:0] tdd_tx_dp_off_2;
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
input [ 7:0] tdd_status;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 1'h0;
reg [31:0] up_scratch = 32'h0;
reg up_rack = 1'h0;
reg [31:0] up_rdata = 32'h0;
reg up_tdd_enable = 1'h0;
reg up_tdd_secondary = 1'h0;
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
reg up_tdd_rx_only = 1'h0;
reg up_tdd_tx_only = 1'h0;
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
reg up_tdd_gated_tx_dmapath = 1'h0;
reg up_tdd_gated_rx_dmapath = 1'h0;
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
reg up_tdd_terminal_type = 1'h0;
fmcomms2/TDD: Update synchronization interface Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 12:14:36 +00:00
reg up_tdd_sync_enable = 1'h0;
ad_tdd_sync: Update the synchronization logic The synchronization interface is a single bidirectional line. Output for Master, input for Slave. The sync_period value is relative to frame length and the digital interface clock. The actual synchronization period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 09:31:58 +00:00
reg [ 7:0] up_tdd_sync_period = 8'h0;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
reg [ 7:0] up_tdd_burst_count = 8'h0;
reg [23:0] up_tdd_counter_init = 24'h0;
reg [23:0] up_tdd_frame_length = 24'h0;
reg [23:0] up_tdd_vco_rx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_1 = 24'h0;
reg [23:0] up_tdd_rx_on_1 = 24'h0;
reg [23:0] up_tdd_rx_off_1 = 24'h0;
reg [23:0] up_tdd_tx_on_1 = 24'h0;
reg [23:0] up_tdd_tx_off_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_2 = 24'h0;
reg [23:0] up_tdd_rx_on_2 = 24'h0;
reg [23:0] up_tdd_rx_off_2 = 24'h0;
reg [23:0] up_tdd_tx_on_2 = 24'h0;
reg [23:0] up_tdd_tx_off_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_2 = 24'h0;
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [ 7:0] up_tdd_status_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h20) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h20) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 1'h0;
up_scratch <= 32'h0;
up_tdd_enable <= 1'h0;
up_tdd_secondary <= 1'h0;
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
up_tdd_rx_only <= 1'h0;
up_tdd_tx_only <= 1'h0;
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
up_tdd_gated_tx_dmapath <= 1'h0;
up_tdd_gated_rx_dmapath <= 1'h0;
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
up_tdd_terminal_type <= 1'h0;
fmcomms2/TDD: Update synchronization interface Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 12:14:36 +00:00
up_tdd_sync_enable <= 1'h0;
ad_tdd_sync: Update the synchronization logic The synchronization interface is a single bidirectional line. Output for Master, input for Slave. The sync_period value is relative to frame length and the digital interface clock. The actual synchronization period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 09:31:58 +00:00
up_tdd_sync_period <= 8'h0;
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_counter_init <= 24'h0;
up_tdd_frame_length <= 24'h0;
up_tdd_burst_count <= 8'h0;
up_tdd_vco_rx_on_1 <= 24'h0;
up_tdd_vco_rx_off_1 <= 24'h0;
up_tdd_vco_tx_on_1 <= 24'h0;
up_tdd_vco_tx_off_1 <= 24'h0;
up_tdd_rx_on_1 <= 24'h0;
up_tdd_rx_off_1 <= 24'h0;
up_tdd_tx_on_1 <= 24'h0;
up_tdd_tx_off_1 <= 24'h0;
up_tdd_tx_dp_on_1 <= 24'h0;
up_tdd_vco_rx_on_2 <= 24'h0;
up_tdd_vco_rx_off_2 <= 24'h0;
up_tdd_vco_tx_on_2 <= 24'h0;
up_tdd_vco_tx_off_2 <= 24'h0;
up_tdd_rx_on_2 <= 24'h0;
up_tdd_rx_off_2 <= 24'h0;
up_tdd_tx_on_2 <= 24'h0;
up_tdd_tx_off_2 <= 24'h0;
up_tdd_tx_dp_on_2 <= 24'h0;
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_enable <= up_wdata[0];
up_tdd_secondary <= up_wdata[1];
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
up_tdd_rx_only <= up_wdata[2];
up_tdd_tx_only <= up_wdata[3];
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
up_tdd_gated_rx_dmapath <= up_wdata[4];
up_tdd_gated_tx_dmapath <= up_wdata[5];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
axi_ad9361&TDD: Update TDD + Delete unnecessary registers + Add the module ad_addsub.v to resolve additions and subtractions inside TDD control + Redefine the burst logic + Redesign the control signal generations + Note: This patch fix the TDD related timing violations
2015-05-13 11:03:01 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_burst_count <= up_wdata[7:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_counter_init <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_frame_length <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
fmcomms2/TDD: Update synchronization interface Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 12:14:36 +00:00
up_tdd_terminal_type <= up_wdata[1];
up_tdd_sync_enable <= up_wdata[0];
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
end
axi_ad9361/tdd: Update the synchronization logic The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 09:21:23 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h15)) begin
ad_tdd_sync: Update the synchronization logic The synchronization interface is a single bidirectional line. Output for Master, input for Slave. The sync_period value is relative to frame length and the digital interface clock. The actual synchronization period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 09:31:58 +00:00
up_tdd_sync_period <= up_wdata[7:0];
axi_ad9361/tdd: Update the synchronization logic The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 09:21:23 +00:00
end
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_rx_on_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_rx_off_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_tx_on_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_tx_off_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_rx_on_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h25)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_rx_off_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h26)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_on_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h27)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_off_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_dp_on_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_dp_off_1 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_rx_on_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h31)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_rx_off_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_tx_on_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_vco_tx_off_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h34)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_rx_on_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h35)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_rx_off_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h36)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_on_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_off_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_dp_on_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
TDD_regmap: Fix addresses
2015-08-06 12:15:50 +00:00
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_tdd_tx_dp_off_2 <= up_wdata[23:0];
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 1'b0;
up_rdata <= 1'b0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
8'h10: up_rdata <= {28'h0, up_tdd_gated_tx_dmapath,
up_tdd_gated_rx_dmapath,
up_tdd_tx_only,
up_tdd_rx_only,
up_tdd_secondary,
up_tdd_enable};
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
8'h12: up_rdata <= { 8'h0, up_tdd_counter_init};
8'h13: up_rdata <= { 8'h0, up_tdd_frame_length};
fmcomms2/TDD: Update synchronization interface Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 12:14:36 +00:00
8'h14: up_rdata <= {30'h0, up_tdd_terminal_type,
up_tdd_sync_enable};
ad_tdd_sync: Update the synchronization logic The synchronization interface is a single bidirectional line. Output for Master, input for Slave. The sync_period value is relative to frame length and the digital interface clock. The actual synchronization period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 09:31:58 +00:00
8'h15: up_rdata <= {24'h0, up_tdd_sync_period};
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
8'h18: up_rdata <= {24'h0, up_tdd_status_s};
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1};
8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1};
8'h22: up_rdata <= { 8'h0, up_tdd_vco_tx_on_1};
8'h23: up_rdata <= { 8'h0, up_tdd_vco_tx_off_1};
8'h24: up_rdata <= { 8'h0, up_tdd_rx_on_1};
8'h25: up_rdata <= { 8'h0, up_tdd_rx_off_1};
8'h26: up_rdata <= { 8'h0, up_tdd_tx_on_1};
8'h27: up_rdata <= { 8'h0, up_tdd_tx_off_1};
8'h28: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1};
8'h29: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1};
8'h30: up_rdata <= { 8'h0, up_tdd_vco_rx_on_2};
8'h31: up_rdata <= { 8'h0, up_tdd_vco_rx_off_2};
8'h32: up_rdata <= { 8'h0, up_tdd_vco_tx_on_2};
8'h33: up_rdata <= { 8'h0, up_tdd_vco_tx_off_2};
8'h34: up_rdata <= { 8'h0, up_tdd_rx_on_2};
8'h35: up_rdata <= { 8'h0, up_tdd_rx_off_2};
8'h36: up_rdata <= { 8'h0, up_tdd_tx_on_2};
8'h37: up_rdata <= { 8'h0, up_tdd_tx_off_2};
8'h38: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2};
8'h39: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2};
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
default: up_rdata <= 32'h0;
endcase
end
end
end
// rf tdd control signal CDC
ad_tdd_sync: Update the synchronization logic The synchronization interface is a single bidirectional line. Output for Master, input for Slave. The sync_period value is relative to frame length and the digital interface clock. The actual synchronization period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 09:31:58 +00:00
up_xfer_cntrl #(.DATA_WIDTH(24)) i_tdd_control (
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_enable,
up_tdd_secondary,
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
up_tdd_rx_only,
up_tdd_tx_only,
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
up_tdd_gated_rx_dmapath,
up_tdd_gated_tx_dmapath,
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
up_tdd_burst_count,
fmcomms2/TDD: Update synchronization interface Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 12:14:36 +00:00
up_tdd_terminal_type,
axi_ad9361/tdd: Update the synchronization logic The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 09:21:23 +00:00
up_tdd_sync_enable,
up_tdd_sync_period
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
}),
ad9361/tdd: Fix generation of tx_valid_* signals In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals. In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 13:21:40 +00:00
.up_xfer_done(),
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
.d_rst(rst),
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
.d_clk(clk),
.d_data_cntrl({tdd_enable,
tdd_secondary,
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 13:46:28 +00:00
tdd_rx_only,
tdd_tx_only,
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 11:10:49 +00:00
tdd_gated_rx_dmapath,
tdd_gated_tx_dmapath,
fmcomms2: Add a synchronization interface for TDD mode. Supported carrier are ZC706 and RFSOM. The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled. By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 11:41:32 +00:00
tdd_burst_count,
fmcomms2/TDD: Update synchronization interface Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 12:14:36 +00:00
tdd_terminal_type,
axi_ad9361/tdd: Update the synchronization logic The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 09:21:23 +00:00
tdd_sync_enable,
tdd_sync_period
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
}));
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
up_xfer_cntrl #(.DATA_WIDTH(528)) i_tdd_counter_values (
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_counter_init,
up_tdd_frame_length,
up_tdd_vco_rx_on_1,
up_tdd_vco_rx_off_1,
up_tdd_vco_tx_on_1,
up_tdd_vco_tx_off_1,
up_tdd_rx_on_1,
up_tdd_rx_off_1,
up_tdd_tx_on_1,
up_tdd_tx_off_1,
up_tdd_tx_dp_on_1,
up_tdd_tx_dp_off_1,
up_tdd_vco_rx_on_2,
up_tdd_vco_rx_off_2,
up_tdd_vco_tx_on_2,
up_tdd_vco_tx_off_2,
up_tdd_rx_on_2,
up_tdd_rx_off_2,
up_tdd_tx_on_2,
up_tdd_tx_off_2,
up_tdd_tx_dp_on_2,
up_tdd_tx_dp_off_2
}),
.up_xfer_done(),
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
.d_rst(rst),
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
.d_clk(clk),
.d_data_cntrl({tdd_counter_init,
tdd_frame_length,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2
}));
up_xfer_status #(.DATA_WIDTH(8)) i_tdd_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status (up_tdd_status_s),
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch https://github.com/analogdevicesinc/hdl/commit/598ece4c8d4ca213b9a8c3dccffc97a314f64381
2015-05-21 10:39:48 +00:00
.d_rst (rst),
axi_ad9361_tdd: Initial commit. Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 09:09:09 +00:00
.d_clk (clk),
.d_data_status (tdd_status));
endmodule
// ***************************************************************************
// ***************************************************************************