79 lines
2.4 KiB
Tcl
79 lines
2.4 KiB
Tcl
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package require qsys
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source ../../scripts/adi_env.tcl
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source ../scripts/adi_ip_intel.tcl
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set_module_property NAME axi_ad7768
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set_module_property DESCRIPTION "AXI AD7768 IP core"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_ad7768
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set_module_property ELABORATION_CALLBACK create_ports
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# source files
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ad_ip_files axi_ad7768 [list \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
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"$ad_hdl_dir/library/common/up_xfer_status.v" \
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"axi_ad7768_if.v" \
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"axi_ad7768.v"]
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# IP parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DEFAULT_VALUE 0
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set_parameter_property ID DISPLAY_NAME "ID"
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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set group "General Configuration"
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ad_ip_parameter NUM_CHANNELS INTEGER 8 true [list \
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DISPLAY_NAME "Number of channels" \
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DISPLAY_UNITS "channels" \
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ALLOWED_RANGES {4 8} \
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GROUP $group \
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]
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# AXI4 Memory Mapped Interface
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 15
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# ad7768_if and axi_gpreg ports
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ad_interface signal adc_dovf input 1 ovf
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ad_interface signal clk_in input 1
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ad_interface signal ready_in input 1
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ad_interface signal data_in input 8
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ad_interface reset adc_reset output 1
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ad_interface clock adc_clk output 1
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ad_interface signal adc_sync output 1 sync
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ad_interface signal adc_valid output 1 valid
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ad_interface signal adc_data output 32 data
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set_interface_property if_adc_reset associatedClock if_adc_clk
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proc create_ports {} {
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set num_channels [get_parameter_value "NUM_CHANNELS"]
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set samples_per_channel 1
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set sample_data_width 32
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set channel_data_width [expr $sample_data_width * $samples_per_channel]
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for {set n 0} {$n < $num_channels} {incr n} {
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add_interface adc_ch_$n conduit end
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add_interface_port adc_ch_$n adc_enable_$n enable Output 1
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add_interface_port adc_ch_$n adc_data_$n data Output $sample_data_width
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add_interface_port adc_ch_$n adc_valid_$n valid Output 1
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set_interface_property adc_ch_$n associatedClock if_adc_clk
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set_interface_property adc_ch_$n associatedReset none
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}
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}
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