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pluto_hdl_adi/library/axi_adrv9001/axi_adrv9001_ip.tcl

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library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
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# ip
scripts: Merge adi_env.tcl into a single file Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
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source ../../scripts/adi_env.tcl
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
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global VIVADO_IP_LIBRARY
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
adi_ip_create axi_adrv9001
adi_ip_files axi_adrv9001 [list \
"$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
"$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \
"$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds_2.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
axi_adrv9001: Add TDD support
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"$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
"$ad_hdl_dir/library/common/ad_tdd_control.v" \
"$ad_hdl_dir/library/common/ad_addsub.v" \
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/ad_pngen.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"adrv9001_rx.v" \
"adrv9001_tx.v" \
"adrv9001_pack.v" \
"adrv9001_aligner4.v" \
"adrv9001_aligner8.v" \
"adrv9001_rx_link.v" \
"adrv9001_tx_link.v" \
"axi_adrv9001_rx.v" \
"axi_adrv9001_rx_channel.v" \
"axi_adrv9001_if.v" \
"axi_adrv9001_tx.v" \
"axi_adrv9001_tx_channel.v" \
"axi_adrv9001_core.v" \
"axi_adrv9001_constr.xdc" \
axi_adrv9001: Add TDD support
2020-08-24 10:34:48 +00:00
"axi_adrv9001_tdd.v" \
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
"axi_adrv9001.v" ]
adi_ip_properties axi_adrv9001
adi_init_bd_tcl
adi_ip_bd axi_adrv9001 "bd/bd.tcl"
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-18 21:10:26 +00:00
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
]
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
axi_adrv9001: Add external sync support The external sync must be synchronous to the reference clock, in order to obtain a deterministic synchronization of the interface.
2021-12-03 14:40:48 +00:00
set cc [ipx::current_core]
ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 $cc
ipx::infer_bus_interface adc_1_clk xilinx.com:signal:clock_rtl:1.0 $cc
ipx::infer_bus_interface adc_2_clk xilinx.com:signal:clock_rtl:1.0 $cc
ipx::infer_bus_interface dac_1_clk xilinx.com:signal:clock_rtl:1.0 $cc
ipx::infer_bus_interface dac_2_clk xilinx.com:signal:clock_rtl:1.0 $cc
ipx::infer_bus_interface adc_1_rst xilinx.com:signal:reset_rtl:1.0 $cc
ipx::infer_bus_interface adc_2_rst xilinx.com:signal:reset_rtl:1.0 $cc
ipx::infer_bus_interface dac_1_rst xilinx.com:signal:reset_rtl:1.0 $cc
ipx::infer_bus_interface dac_2_rst xilinx.com:signal:reset_rtl:1.0 $cc
ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_1_rst -of_objects $cc]
ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_2_rst -of_objects $cc]
ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_1_rst -of_objects $cc]
ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_2_rst -of_objects $cc]
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
axi_adrv9001: Hide disabled interfaces Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-25 14:00:44 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INDEPENDENT_1R1T_SUPPORT')) == 1 && spirit:decode(id('MODELPARAM_VALUE.DISABLE_TX2_SSI')) == 0} \
axi_adrv9001: Add external sync support The external sync must be synchronous to the reference clock, in order to obtain a deterministic synchronization of the interface.
2021-12-03 14:40:48 +00:00
[ipx::get_ports dac_2* -of_objects $cc]
axi_adrv9001: Hide disabled interfaces Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-25 14:00:44 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INDEPENDENT_1R1T_SUPPORT')) == 1 && spirit:decode(id('MODELPARAM_VALUE.DISABLE_RX2_SSI')) == 0} \
axi_adrv9001: Add external sync support The external sync must be synchronous to the reference clock, in order to obtain a deterministic synchronization of the interface.
2021-12-03 14:40:48 +00:00
[ipx::get_ports adc_2* -of_objects $cc]
axi_adrv9001: Hide disabled interfaces Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-25 14:00:44 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.DISABLE_TX2_SSI')) == 0} \
axi_adrv9001: Add external sync support The external sync must be synchronous to the reference clock, in order to obtain a deterministic synchronization of the interface.
2021-12-03 14:40:48 +00:00
[ipx::get_ports *tx2_* -of_objects $cc]
axi_adrv9001: Hide disabled interfaces Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-25 14:00:44 +00:00
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.DISABLE_RX2_SSI')) == 0} \
axi_adrv9001: Add external sync support The external sync must be synchronous to the reference clock, in order to obtain a deterministic synchronization of the interface.
2021-12-03 14:40:48 +00:00
[ipx::get_ports *rx2_* -of_objects $cc]
set_property driver_value 0 [ipx::get_ports *_sync_in* -of_objects $cc]
## Customize XGUI layout
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
ipgui::add_param -name "EXT_SYNC" -component $cc -parent $page0
set_property -dict [list \
"display_name" "External sync" \
"tooltip" "NOTE: If active enables the external synchronization features for Rx and Tx. The external sync signals must be synchronous with to ref_clk" \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "EXT_SYNC" -component $cc]
adi_set_ports_dependency "adc_sync_in" \
"(spirit:decode(id('MODELPARAM_VALUE.EXT_SYNC')) == 1)"
adi_set_ports_dependency "dac_sync_in" \
"(spirit:decode(id('MODELPARAM_VALUE.EXT_SYNC')) == 1)"
axi_adrv9001: Hide disabled interfaces Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-25 14:00:44 +00:00
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
adi_add_auto_fpga_spec_params
axi_adrv9001: Add external sync support The external sync must be synchronous to the reference clock, in order to obtain a deterministic synchronization of the interface.
2021-12-03 14:40:48 +00:00
ipx::create_xgui_files $cc
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
axi_adrv9001: Add external sync support The external sync must be synchronous to the reference clock, in order to obtain a deterministic synchronization of the interface.
2021-12-03 14:40:48 +00:00
ipx::save_core $cc