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pluto_hdl_adi/library/axi_dmac/Makefile

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makefile: added
2015-04-01 20:26:28 +00:00
####################################################################################
Makefiles: Update header with the appropriate license
2021-09-15 15:03:11 +00:00
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
makefile: added
2015-04-01 20:26:28 +00:00
## Auto-generated, do not modify!
####################################################################################
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
LIBRARY_NAME := axi_dmac
makefile: added
2015-04-01 20:26:28 +00:00
Makefile: update makefiles
2018-12-19 09:35:31 +00:00
GENERIC_DEPS += ../common/ad_mem_asym.v
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += 2d_transfer.v
GENERIC_DEPS += address_generator.v
GENERIC_DEPS += axi_dmac.v
axi_dmac: Rework data store-and-forward buffer Currently the DMAC uses a simple FIFO as the store-and-forward buffer. The FIFO handshaking is beat based whereas the remainder of the DMAC is burst based. This means that additional control signals have to be combined with the FIFO handshaking signal to generate the external handshaking signals. Re-work the store-and-forward buffer to utilize a BRAM that is subdivided into N segments. Where N is the maximum number of bursts that can be stored in the buffer and each segment has the size of the maximum burst length. Each segment stores the data associated with one burst and even when the burst is shorter than the maximum burst length the next burst will be stored in the next segment. The new store-and-forward buffer takes care of generating all the handshaking signals. This means handshaking is generated in a central place and does not have to be combined from multiple data-paths simplifying the overall logic. The new store-and-forward buffer also takes care of data width up- and down-sizing in case that the source and sink modules have a different data width. This tighter integration will allow future enhancements like using asymmetric memory. This re-work lays the foundation of future enhancements to the DMA like support for un-aligned transfers and early transfer abort which would have been much more difficult to implement with the previous architecture. In addition it significantly reduces the resource utilization of the store-and-forward buffer and allows for better timing due to reduced combinatorial path lengths. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-09 16:02:41 +00:00
GENERIC_DEPS += axi_dmac_burst_memory.v
axi_dmac: Split register map into separate sub-module Split the register map code into a separate sub-module instead of having it as part of the top-level axi_dmac.v file. This makes it easier to component test the register map behavior independently from the DMA transfer logic. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-05 05:57:38 +00:00
GENERIC_DEPS += axi_dmac_regmap.v
GENERIC_DEPS += axi_dmac_regmap_request.v
axi_dmac: Rework transfer shutdown The DMAC allows a transfer to be aborted. When a transfer is aborted the DMAC shuts down as fast as possible while still completing any pending transactions as required by the protocol specifications of the port. E.g. for AXI-MM this means to complete all outstanding bursts. Once the DMAC has entered an idle state a special synchronization signal is send to all modules. This synchronization signal instructs them to flush the pipeline and remove any stale data and metadata associated with the aborted transfer. Once all data has been flushed the DMAC enters the shutdown state and is ready for the next transfer. In addition each module has a reset that resets the modules state and is used at system startup to bring them into a consistent state. Re-work the shutdown process to instead of flushing the pipeline re-use the startup reset signal also for shutdown. To manage the reset signal generation introduce the reset manager module. It contains a state machine that will assert the reset signals in the correct order and for the appropriate duration in case of a transfer shutdown. The reset signal is asserted in all domains until it has been asserted for at least 4 clock cycles in the slowest domain. This ensures that the reset signal is not de-asserted in the faster domains before the slower domains have had a chance to process the reset signal. In addition the reset signal is de-asserted in the opposite direction of the data flow. This ensures that the data sink is ready to receive data before the data source can start sending data. This simplifies the internal handshaking. This approach has multiple advantages. * Issuing a reset and removing all state takes less time than explicitly flushing one sample per clock cycle at a time. * It simplifies the logic in the faster clock domains at the expense of more complicated logic in the slower control clock domain. This allows for higher fMax on the data paths. * Less signals to synchronize from the control domain to the data domains The implementation of the pause mode has also slightly changed. Pause is now a simple disable of the data domains. When the transfer is resumed after a pause the data domains are re-enabled and continue at their previous state. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-21 14:02:44 +00:00
GENERIC_DEPS += axi_dmac_reset_manager.v
axi_dmac: Rework data store-and-forward buffer Currently the DMAC uses a simple FIFO as the store-and-forward buffer. The FIFO handshaking is beat based whereas the remainder of the DMAC is burst based. This means that additional control signals have to be combined with the FIFO handshaking signal to generate the external handshaking signals. Re-work the store-and-forward buffer to utilize a BRAM that is subdivided into N segments. Where N is the maximum number of bursts that can be stored in the buffer and each segment has the size of the maximum burst length. Each segment stores the data associated with one burst and even when the burst is shorter than the maximum burst length the next burst will be stored in the next segment. The new store-and-forward buffer takes care of generating all the handshaking signals. This means handshaking is generated in a central place and does not have to be combined from multiple data-paths simplifying the overall logic. The new store-and-forward buffer also takes care of data width up- and down-sizing in case that the source and sink modules have a different data width. This tighter integration will allow future enhancements like using asymmetric memory. This re-work lays the foundation of future enhancements to the DMA like support for un-aligned transfers and early transfer abort which would have been much more difficult to implement with the previous architecture. In addition it significantly reduces the resource utilization of the store-and-forward buffer and allows for better timing due to reduced combinatorial path lengths. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-09 16:02:41 +00:00
GENERIC_DEPS += axi_dmac_resize_dest.v
GENERIC_DEPS += axi_dmac_resize_src.v
axi_dmac: preparation work for reporting length of partial transfers Length of partial transfers are stored in a queue for SW reads. The presence of partial transfer is indicated by a status bit. The reporting can be enabled by a control bit. The progress of any transfer can be followed by a debug register.
2018-08-10 14:47:21 +00:00
GENERIC_DEPS += axi_dmac_response_manager.v
axi_dmac: Split transfer handling into separate sub-module Move the transfer logic, including the 2d module, into its own sub-module. This allows testing of the full transfer logic independently of the register map logic. The top-level module now only instantiates the register map and transfer module, but does not have any logic on its own. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-05 05:57:38 +00:00
GENERIC_DEPS += axi_dmac_transfer.v
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
GENERIC_DEPS += axi_register_slice.v
GENERIC_DEPS += data_mover.v
GENERIC_DEPS += dest_axi_mm.v
GENERIC_DEPS += dest_axi_stream.v
GENERIC_DEPS += dest_fifo_inf.v
axi_dmac: renamed .h files to .vh Vivado recognises .h files as C header files, the expected extension for Verilog Header is .vh This causes issues in simulating block designs since these files won't be exported for the simulation even if they are part of the simulation fileset.
2018-06-28 11:14:14 +00:00
GENERIC_DEPS += inc_id.vh
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
GENERIC_DEPS += request_arb.v
GENERIC_DEPS += request_generator.v
axi_dmac: renamed .h files to .vh Vivado recognises .h files as C header files, the expected extension for Verilog Header is .vh This causes issues in simulating block designs since these files won't be exported for the simulation even if they are part of the simulation fileset.
2018-06-28 11:14:14 +00:00
GENERIC_DEPS += resp.vh
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
GENERIC_DEPS += response_generator.v
GENERIC_DEPS += response_handler.v
GENERIC_DEPS += splitter.v
GENERIC_DEPS += src_axi_mm.v
GENERIC_DEPS += src_axi_stream.v
GENERIC_DEPS += src_fifo_inf.v
updated makefiles
2016-12-09 21:06:41 +00:00
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
XILINX_DEPS += axi_dmac_constr.ttcl
XILINX_DEPS += axi_dmac_ip.tcl
Makefile: update makefiles
2018-12-19 09:35:31 +00:00
XILINX_DEPS += axi_dmac_pkg_sv.ttcl
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
XILINX_DEPS += bd/bd.tcl
makefile: added
2015-04-01 20:26:28 +00:00
Move Altera IP core dependency tracking to library Makefiles Currently the individual IP core dependencies are tracked inside the library Makefile for Xilinx IPs and the project Makefiles only reference the IP cores. For Altera on the other hand the individual dependencies are tracked inside the project Makefile. This leads to a lot of duplicated lists and also means that the project Makefiles need to be regenerated when one of the IP cores changes their files. Change the Altera projects to a similar scheme than the Xilinx projects. The projects themselves only reference the library as a whole as their dependency while the library Makefile references the individual source dependencies. Since on Altera there is no target that has to be generated create a dummy target called ".timestamp_altera" who's only purpose is to have a timestamp that is greater or equal to the timestamp of all of the IP core files. This means the project Makefile can have a dependency on this file and make sure that the project will be rebuild if any of the files in the library changes. This patch contains quite a bit of churn, but hopefully it reduces the amount of churn in the future when modifying Altera IP cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-27 09:21:09 +00:00
XILINX_DEPS += ../interfaces/fifo_rd.xml
XILINX_DEPS += ../interfaces/fifo_rd_rtl.xml
XILINX_DEPS += ../interfaces/fifo_wr.xml
XILINX_DEPS += ../interfaces/fifo_wr_rtl.xml
XILINX_LIB_DEPS += util_axis_fifo
XILINX_LIB_DEPS += util_cdc
all: Rename altera to intel
2018-08-13 13:59:02 +00:00
INTEL_DEPS += ../util_axis_fifo/util_axis_fifo.v
Makefile: Fix misc makefiles from projects and library
2021-09-30 13:20:02 +00:00
INTEL_DEPS += ../util_axis_fifo/util_axis_fifo_address_generator.v
all: Rename altera to intel
2018-08-13 13:59:02 +00:00
INTEL_DEPS += ../util_cdc/sync_bits.v
INTEL_DEPS += ../util_cdc/sync_event.v
INTEL_DEPS += axi_dmac_constr.sdc
INTEL_DEPS += axi_dmac_hw.tcl
makefile: added
2015-04-01 20:26:28 +00:00
Regenerate library Makefiles using the new shared Makefile include This reduces the amount of boilerplate code that is present in these Makefiles by a lot. It also makes it possible to update the Makefile rules in future without having to re-generate all the Makefiles. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-23 09:19:51 +00:00
include ../scripts/library.mk