2020-08-24 10:34:48 +00:00
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_adrv9001_tdd #(
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parameter ID = 0,
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parameter BASE_ADDRESS = 6'h20
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) (
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// clock
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input clk,
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input rst,
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// control signals from the tdd control
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output tdd_rx_vco_en,
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output tdd_tx_vco_en,
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output tdd_rx_rf_en,
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output tdd_tx_rf_en,
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// status signal
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output tdd_enabled,
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input [ 7:0] tdd_status,
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// sync signal
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input tdd_sync,
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output reg tdd_sync_cntr,
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// tx/rx data flow control
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2021-01-05 07:17:00 +00:00
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output reg tdd_tx_valid = 1'b1,
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output reg tdd_rx_valid = 1'b1,
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2020-08-24 10:34:48 +00:00
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack);
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// internal signals
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wire tdd_enable_s;
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wire tdd_secondary_s;
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wire [ 7:0] tdd_burst_count_s;
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wire tdd_rx_only_s;
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wire tdd_tx_only_s;
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wire tdd_gated_rx_dmapath_s;
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wire tdd_gated_tx_dmapath_s;
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wire [23:0] tdd_counter_init_s;
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wire [23:0] tdd_frame_length_s;
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wire tdd_terminal_type_s;
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wire tdd_sync_enable_s;
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wire [23:0] tdd_vco_rx_on_1_s;
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wire [23:0] tdd_vco_rx_off_1_s;
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wire [23:0] tdd_vco_tx_on_1_s;
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wire [23:0] tdd_vco_tx_off_1_s;
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wire [23:0] tdd_rx_on_1_s;
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wire [23:0] tdd_rx_off_1_s;
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wire [23:0] tdd_rx_dp_on_1_s;
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wire [23:0] tdd_rx_dp_off_1_s;
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wire [23:0] tdd_tx_on_1_s;
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wire [23:0] tdd_tx_off_1_s;
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wire [23:0] tdd_tx_dp_on_1_s;
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wire [23:0] tdd_tx_dp_off_1_s;
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wire [23:0] tdd_vco_rx_on_2_s;
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wire [23:0] tdd_vco_rx_off_2_s;
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wire [23:0] tdd_vco_tx_on_2_s;
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wire [23:0] tdd_vco_tx_off_2_s;
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wire [23:0] tdd_rx_on_2_s;
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wire [23:0] tdd_rx_off_2_s;
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wire [23:0] tdd_rx_dp_on_2_s;
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wire [23:0] tdd_rx_dp_off_2_s;
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wire [23:0] tdd_tx_on_2_s;
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wire [23:0] tdd_tx_off_2_s;
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wire [23:0] tdd_tx_dp_on_2_s;
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wire [23:0] tdd_tx_dp_off_2_s;
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wire [23:0] tdd_counter_status;
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wire tdd_rx_dp_en_s;
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wire tdd_tx_dp_en_s;
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assign tdd_enabled = tdd_enable_s;
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// syncronization control signal
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always @(posedge clk) begin
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if (tdd_enable_s == 1'b1) begin
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tdd_sync_cntr <= ~tdd_terminal_type_s;
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end else begin
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tdd_sync_cntr <= 1'b0;
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end
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end
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// tx/rx data flow control
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always @(posedge clk) begin
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if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
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tdd_tx_valid <= tdd_tx_dp_en_s;
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end else begin
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tdd_tx_valid <= 1'b1;
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end
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end
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always @(posedge clk) begin
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if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
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tdd_rx_valid <= tdd_rx_dp_en_s;
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end else begin
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tdd_rx_valid <= 1'b1;
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end
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end
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// instantiations
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up_tdd_cntrl #(
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.BASE_ADDRESS (BASE_ADDRESS)
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) i_up_tdd_cntrl(
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.clk(clk),
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.rst(rst),
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.tdd_enable(tdd_enable_s),
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.tdd_secondary(tdd_secondary_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_tx_only(tdd_tx_only_s),
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.tdd_rx_only(tdd_rx_only_s),
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.tdd_gated_rx_dmapath(tdd_gated_rx_dmapath_s),
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.tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s),
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_terminal_type(tdd_terminal_type_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
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.tdd_rx_on_1(tdd_rx_on_1_s),
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.tdd_rx_off_1(tdd_rx_off_1_s),
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.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
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.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
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.tdd_tx_on_1(tdd_tx_on_1_s),
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.tdd_tx_off_1(tdd_tx_off_1_s),
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.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
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.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
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.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
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.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
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.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
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.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
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.tdd_rx_on_2(tdd_rx_on_2_s),
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.tdd_rx_off_2(tdd_rx_off_2_s),
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.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
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.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
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.tdd_tx_on_2(tdd_tx_on_2_s),
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.tdd_tx_off_2(tdd_tx_off_2_s),
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.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
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.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
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.tdd_status(tdd_status),
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_wack(up_wack),
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.up_rreq(up_rreq),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata),
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.up_rack(up_rack));
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// the TX_DATA_PATH_DELAY and CONTROL_PATH_DELAY are specificly defined
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// for the axi_adrv9001 core
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ad_tdd_control #(
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.TX_DATA_PATH_DELAY(),
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.CONTROL_PATH_DELAY())
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i_tdd_control(
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.clk(clk),
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.rst(rst),
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.tdd_enable(tdd_enable_s),
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.tdd_secondary(tdd_secondary_s),
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_rx_only(tdd_rx_only_s),
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.tdd_tx_only(tdd_tx_only_s),
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.tdd_sync (tdd_sync),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
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.tdd_rx_on_1(tdd_rx_on_1_s),
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.tdd_rx_off_1(tdd_rx_off_1_s),
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.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
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.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
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.tdd_tx_on_1(tdd_tx_on_1_s),
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.tdd_tx_off_1(tdd_tx_off_1_s),
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.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
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.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
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.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
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.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
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.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
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.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
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.tdd_rx_on_2(tdd_rx_on_2_s),
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.tdd_rx_off_2(tdd_rx_off_2_s),
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.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
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.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
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.tdd_tx_on_2(tdd_tx_on_2_s),
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.tdd_tx_off_2(tdd_tx_off_2_s),
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.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
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.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
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.tdd_rx_dp_en(tdd_rx_dp_en_s),
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.tdd_tx_dp_en(tdd_tx_dp_en_s),
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.tdd_rx_vco_en(tdd_rx_vco_en),
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.tdd_tx_vco_en(tdd_tx_vco_en),
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.tdd_rx_rf_en(tdd_rx_rf_en),
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.tdd_tx_rf_en(tdd_tx_rf_en),
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.tdd_counter_status(tdd_counter_status));
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endmodule
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