2015-02-20 14:15:01 +00:00
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
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DDR_odt,
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DDR_ras_n,
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DDR_reset_n,
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DDR_we_n,
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eth1_rgmii_rd,
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eth1_rgmii_rx_ctl,
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eth1_rgmii_rxc,
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eth1_rgmii_td,
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eth1_rgmii_tx_ctl,
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eth1_rgmii_txc,
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eth2_rgmii_rd,
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eth2_rgmii_rx_ctl,
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eth2_rgmii_rxc,
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eth2_rgmii_td,
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eth2_rgmii_tx_ctl,
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eth2_rgmii_txc,
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eth_mdio_io,
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eth_mdio_mdc,
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eth_phy_rst_n,
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FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp,
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FIXED_IO_mio,
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FIXED_IO_ps_clk,
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FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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position_m1_i,
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position_m2_i,
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adc_clk_o,
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adc_m1_ia_dat_i,
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adc_m1_ib_dat_i,
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adc_m1_vbus_dat_i,
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fmc_m1_en_o,
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fmc_m2_en_o,
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adc_m2_ia_dat_i,
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adc_m2_ib_dat_i,
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adc_m2_vbus_dat_i,
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pwm_m1_ah_o,
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pwm_m1_al_o,
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pwm_m1_bh_o,
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pwm_m1_bl_o,
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pwm_m1_ch_o,
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pwm_m1_cl_o,
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pwm_m1_dh_o,
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pwm_m1_dl_o,
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pwm_m2_ah_o,
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pwm_m2_al_o,
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pwm_m2_bh_o,
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pwm_m2_bl_o,
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pwm_m2_ch_o,
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pwm_m2_cl_o,
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pwm_m2_dh_o,
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pwm_m2_dl_o,
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vt_enable,
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2015-03-02 14:44:42 +00:00
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vauxn0,
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2015-02-20 14:15:01 +00:00
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vauxn8,
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vauxp0,
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vauxp8,
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2015-03-02 14:44:42 +00:00
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/* muxaddr_out,*/
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2015-02-20 14:15:01 +00:00
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i2s_mclk,
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i2s_bclk,
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i2s_lrclk,
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i2s_sdata_out,
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i2s_sdata_in,
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spdif,
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iic_scl,
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iic_sda,
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iic_mux_scl,
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iic_mux_sda,
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iic_ee2_scl_io,
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iic_ee2_sda_io,
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fmc_spi1_sel1_rdc,
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fmc_spi1_miso,
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fmc_spi1_mosi,
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fmc_spi1_sck,
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fmc_sample_n,
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gpo,
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gpi,
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otg_vbusoc);
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inout [14:0] DDR_addr;
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inout [ 2:0] DDR_ba;
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inout DDR_cas_n;
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inout DDR_ck_n;
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inout DDR_ck_p;
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inout DDR_cke;
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inout DDR_cs_n;
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inout [ 3:0] DDR_dm;
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inout [31:0] DDR_dq;
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inout [ 3:0] DDR_dqs_n;
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inout [ 3:0] DDR_dqs_p;
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inout DDR_odt;
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inout DDR_ras_n;
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inout DDR_reset_n;
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inout DDR_we_n;
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input [3:0] eth1_rgmii_rd;
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input eth1_rgmii_rx_ctl;
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input eth1_rgmii_rxc;
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output [3:0] eth1_rgmii_td;
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output eth1_rgmii_tx_ctl;
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output eth1_rgmii_txc;
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input [3:0] eth2_rgmii_rd;
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input eth2_rgmii_rx_ctl;
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input eth2_rgmii_rxc;
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output [3:0] eth2_rgmii_td;
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output eth2_rgmii_tx_ctl;
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output eth2_rgmii_txc;
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inout eth_mdio_io;
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output eth_mdio_mdc;
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output eth_phy_rst_n;
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inout FIXED_IO_ddr_vrn;
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inout FIXED_IO_ddr_vrp;
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inout [53:0] FIXED_IO_mio;
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inout FIXED_IO_ps_clk;
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inout FIXED_IO_ps_porb;
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inout FIXED_IO_ps_srstb;
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inout [31:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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input [2:0] position_m1_i;
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input [2:0] position_m2_i;
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output adc_clk_o;
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output fmc_m1_en_o;
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input adc_m1_ia_dat_i;
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input adc_m1_ib_dat_i;
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input adc_m1_vbus_dat_i;
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output fmc_m2_en_o;
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input adc_m2_ia_dat_i;
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input adc_m2_ib_dat_i;
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input adc_m2_vbus_dat_i;
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output pwm_m1_ah_o;
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output pwm_m1_al_o;
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output pwm_m1_bh_o;
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output pwm_m1_bl_o;
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output pwm_m1_ch_o;
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output pwm_m1_cl_o;
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output pwm_m1_dh_o;
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output pwm_m1_dl_o;
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output pwm_m2_ah_o;
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output pwm_m2_al_o;
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output pwm_m2_bh_o;
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output pwm_m2_bl_o;
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output pwm_m2_ch_o;
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output pwm_m2_cl_o;
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output pwm_m2_dh_o;
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output pwm_m2_dl_o;
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2015-03-02 14:44:42 +00:00
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2015-02-20 14:15:01 +00:00
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output vt_enable;
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2015-03-02 14:44:42 +00:00
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input vauxn0;
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2015-02-20 14:15:01 +00:00
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input vauxn8;
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input vauxp0;
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input vauxp8;
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2015-03-02 14:44:42 +00:00
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/* output [ 3:0] muxaddr_out;*/
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2015-02-20 14:15:01 +00:00
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output spdif;
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output i2s_mclk;
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output i2s_bclk;
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output i2s_lrclk;
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output i2s_sdata_out;
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input i2s_sdata_in;
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inout iic_scl;
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inout iic_sda;
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inout [ 1:0] iic_mux_scl;
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inout [ 1:0] iic_mux_sda;
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inout iic_ee2_scl_io;
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inout iic_ee2_sda_io;
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output fmc_spi1_sel1_rdc;
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input fmc_spi1_miso;
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output fmc_spi1_mosi;
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output fmc_spi1_sck;
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output fmc_sample_n;
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output [ 3:0] gpo;
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input [ 1:0] gpi;
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input otg_vbusoc;
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// internal signals
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wire [34:0] gpio_i;
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wire [34:0] gpio_o;
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wire [34:0] gpio_t;
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wire [ 1:0] iic_mux_scl_i_s;
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wire [ 1:0] iic_mux_scl_o_s;
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wire iic_mux_scl_t_s;
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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wire [15:0] ps_intrs;
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wire refclk;
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wire refclk_rst;
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wire eth_mdio_o;
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wire eth_mdio_i;
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wire eth_mdio_t;
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reg idelayctrl_reset;
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reg [ 3:0] idelay_reset_cnt;
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// assignments
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assign fmc_sample_n = gpio_o[32];
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assign gpio_i[34:33] = gpi[1:0];
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assign vt_enable = 1'b1;
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assign pwm_m1_dh_o = 1'b0;
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assign pwm_m1_dl_o = 1'b0;
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assign pwm_m2_dh_o = 1'b0;
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assign pwm_m2_dl_o = 1'b0;
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// instantiations
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ad_iobuf #(
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.DATA_WIDTH(32))
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i_gpio_bd (
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.dt(gpio_t[31:0]),
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.di(gpio_o[31:0]),
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.do(gpio_i[31:0]),
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.dio(gpio_bd));
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ad_iobuf #(
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.DATA_WIDTH(2))
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i_iic_mux_scl (
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.dt({iic_mux_scl_t_s, iic_mux_scl_t_s}),
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.di(iic_mux_scl_o_s),
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.do(iic_mux_scl_i_s),
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.dio(iic_mux_scl));
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ad_iobuf #(
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.DATA_WIDTH(2))
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i_iic_mux_sda (
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.dt({iic_mux_sda_t_s, iic_mux_sda_t_s}),
|
|
|
|
|
.di(iic_mux_sda_o_s),
|
|
|
|
|
.do(iic_mux_sda_i_s),
|
|
|
|
|
.dio(iic_mux_sda));
|
|
|
|
|
|
|
|
|
|
ad_iobuf #(
|
|
|
|
|
.DATA_WIDTH(1))
|
|
|
|
|
i_mdio_io (
|
|
|
|
|
.dt(eth_mdio_t),
|
|
|
|
|
.di(eth_mdio_o),
|
|
|
|
|
.do(eth_mdio_i),
|
|
|
|
|
.dio(eth_mdio_io));
|
|
|
|
|
|
|
|
|
|
always @(posedge refclk) begin
|
|
|
|
|
if (refclk_rst == 1'b1) begin
|
|
|
|
|
idelay_reset_cnt <= 4'h0;
|
|
|
|
|
idelayctrl_reset <= 1'b1;
|
|
|
|
|
end else begin
|
|
|
|
|
idelayctrl_reset <= 1'b1;
|
|
|
|
|
case (idelay_reset_cnt)
|
|
|
|
|
4'h0: idelay_reset_cnt <= 4'h1;
|
|
|
|
|
4'h1: idelay_reset_cnt <= 4'h2;
|
|
|
|
|
4'h2: idelay_reset_cnt <= 4'h3;
|
|
|
|
|
4'h3: idelay_reset_cnt <= 4'h4;
|
|
|
|
|
4'h4: idelay_reset_cnt <= 4'h5;
|
|
|
|
|
4'h5: idelay_reset_cnt <= 4'h6;
|
|
|
|
|
4'h6: idelay_reset_cnt <= 4'h7;
|
|
|
|
|
4'h7: idelay_reset_cnt <= 4'h8;
|
|
|
|
|
4'h8: idelay_reset_cnt <= 4'h9;
|
|
|
|
|
4'h9: idelay_reset_cnt <= 4'ha;
|
|
|
|
|
4'ha: idelay_reset_cnt <= 4'hb;
|
|
|
|
|
4'hb: idelay_reset_cnt <= 4'hc;
|
|
|
|
|
4'hc: idelay_reset_cnt <= 4'hd;
|
|
|
|
|
4'hd: idelay_reset_cnt <= 4'he;
|
|
|
|
|
default: begin
|
|
|
|
|
idelay_reset_cnt <= 4'he;
|
|
|
|
|
idelayctrl_reset <= 1'b0;
|
|
|
|
|
end
|
|
|
|
|
endcase
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
IDELAYCTRL dlyctrl (
|
|
|
|
|
.RDY(),
|
|
|
|
|
.REFCLK(refclk),
|
|
|
|
|
.RST(idelayctrl_reset));
|
|
|
|
|
|
|
|
|
|
system_wrapper i_system_wrapper (
|
|
|
|
|
.DDR_addr (DDR_addr),
|
|
|
|
|
.DDR_ba (DDR_ba),
|
|
|
|
|
.DDR_cas_n (DDR_cas_n),
|
|
|
|
|
.DDR_ck_n (DDR_ck_n),
|
|
|
|
|
.DDR_ck_p (DDR_ck_p),
|
|
|
|
|
.DDR_cke (DDR_cke),
|
|
|
|
|
.DDR_cs_n (DDR_cs_n),
|
|
|
|
|
.DDR_dm (DDR_dm),
|
|
|
|
|
.DDR_dq (DDR_dq),
|
|
|
|
|
.DDR_dqs_n (DDR_dqs_n),
|
|
|
|
|
.DDR_dqs_p (DDR_dqs_p),
|
|
|
|
|
.DDR_odt (DDR_odt),
|
|
|
|
|
.DDR_ras_n (DDR_ras_n),
|
|
|
|
|
.DDR_reset_n (DDR_reset_n),
|
|
|
|
|
.DDR_we_n (DDR_we_n),
|
|
|
|
|
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
|
|
|
|
|
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
|
|
|
|
|
.FIXED_IO_mio (FIXED_IO_mio),
|
|
|
|
|
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
|
|
|
|
|
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
|
|
|
|
|
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
|
|
|
|
|
.GPIO_I (gpio_i),
|
|
|
|
|
.GPIO_O (gpio_o),
|
|
|
|
|
.GPIO_T (gpio_t),
|
|
|
|
|
|
|
|
|
|
.eth1_rgmii_rd(eth1_rgmii_rd),
|
|
|
|
|
.eth1_rgmii_rx_ctl(eth1_rgmii_rx_ctl),
|
|
|
|
|
.eth1_rgmii_rxc(eth1_rgmii_rxc),
|
|
|
|
|
.eth1_rgmii_td(eth1_rgmii_td),
|
|
|
|
|
.eth1_rgmii_tx_ctl(eth1_rgmii_tx_ctl),
|
|
|
|
|
.eth1_rgmii_txc(eth1_rgmii_txc),
|
|
|
|
|
|
|
|
|
|
.eth2_rgmii_rd(eth2_rgmii_rd),
|
|
|
|
|
.eth2_rgmii_rx_ctl(eth2_rgmii_rx_ctl),
|
|
|
|
|
.eth2_rgmii_rxc(eth2_rgmii_rxc),
|
|
|
|
|
.eth2_rgmii_td(eth2_rgmii_td),
|
|
|
|
|
.eth2_rgmii_tx_ctl(eth2_rgmii_tx_ctl),
|
|
|
|
|
.eth2_rgmii_txc(eth2_rgmii_txc),
|
|
|
|
|
|
|
|
|
|
.eth_phy_rst_n(eth_phy_rst_n),
|
|
|
|
|
.eth_mdio_o(eth_mdio_o),
|
|
|
|
|
.eth_mdio_t(eth_mdio_t),
|
|
|
|
|
.eth_mdio_i(eth_mdio_i),
|
|
|
|
|
.eth_mdio_mdc(eth_mdio_mdc),
|
|
|
|
|
|
|
|
|
|
.hdmi_data (hdmi_data),
|
|
|
|
|
.hdmi_data_e (hdmi_data_e),
|
|
|
|
|
.hdmi_hsync (hdmi_hsync),
|
|
|
|
|
.hdmi_out_clk (hdmi_out_clk),
|
|
|
|
|
.hdmi_vsync (hdmi_vsync),
|
|
|
|
|
.position_m1_i(position_m1_i),
|
|
|
|
|
.position_m2_i(position_m2_i),
|
|
|
|
|
.adc_clk_o(adc_clk_o),
|
|
|
|
|
.fmc_m1_en_o(fmc_m1_en_o),
|
|
|
|
|
.adc_m1_ia_dat_i(adc_m1_ia_dat_i),
|
|
|
|
|
.adc_m1_ib_dat_i(adc_m1_ib_dat_i),
|
|
|
|
|
.adc_m1_vbus_dat_i(adc_m1_vbus_dat_i),
|
|
|
|
|
.fmc_m2_en_o(fmc_m2_en_o),
|
|
|
|
|
.adc_m2_ia_dat_i(adc_m2_ia_dat_i),
|
|
|
|
|
.adc_m2_ib_dat_i(adc_m2_ib_dat_i),
|
|
|
|
|
.adc_m2_vbus_dat_i(adc_m2_vbus_dat_i),
|
|
|
|
|
.gpo_o(gpo),
|
|
|
|
|
.pwm_m1_ah_o(pwm_m1_ah_o),
|
|
|
|
|
.pwm_m1_al_o(pwm_m1_al_o),
|
|
|
|
|
.pwm_m1_bh_o(pwm_m1_bh_o),
|
|
|
|
|
.pwm_m1_bl_o(pwm_m1_bl_o),
|
|
|
|
|
.pwm_m1_ch_o(pwm_m1_ch_o),
|
|
|
|
|
.pwm_m1_cl_o(pwm_m1_cl_o),
|
|
|
|
|
.pwm_m2_ah_o(pwm_m2_ah_o),
|
|
|
|
|
.pwm_m2_al_o(pwm_m2_al_o),
|
|
|
|
|
.pwm_m2_bh_o(pwm_m2_bh_o),
|
|
|
|
|
.pwm_m2_bl_o(pwm_m2_bl_o),
|
|
|
|
|
.pwm_m2_ch_o(pwm_m2_ch_o),
|
|
|
|
|
.pwm_m2_cl_o(pwm_m2_cl_o),
|
2015-03-02 14:44:42 +00:00
|
|
|
.Vaux0_v_n(vauxn0),
|
2015-02-20 14:15:01 +00:00
|
|
|
.Vaux0_v_p(vauxp0),
|
|
|
|
|
.Vaux8_v_n(vauxn8),
|
|
|
|
|
.Vaux8_v_p(vauxp8),
|
2015-03-02 14:44:42 +00:00
|
|
|
/*.muxaddr_out(muxaddr_out),*/
|
2015-02-20 14:15:01 +00:00
|
|
|
.i2s_bclk (i2s_bclk),
|
|
|
|
|
.i2s_lrclk (i2s_lrclk),
|
|
|
|
|
.i2s_mclk (i2s_mclk),
|
|
|
|
|
.i2s_sdata_in (i2s_sdata_in),
|
|
|
|
|
.i2s_sdata_out (i2s_sdata_out),
|
|
|
|
|
.iic_fmc_scl_io (iic_scl),
|
|
|
|
|
.iic_fmc_sda_io (iic_sda),
|
|
|
|
|
.iic_mux_scl_I (iic_mux_scl_i_s),
|
|
|
|
|
.iic_mux_scl_O (iic_mux_scl_o_s),
|
|
|
|
|
.iic_mux_scl_T (iic_mux_scl_t_s),
|
|
|
|
|
.iic_mux_sda_I (iic_mux_sda_i_s),
|
|
|
|
|
.iic_mux_sda_O (iic_mux_sda_o_s),
|
|
|
|
|
.iic_mux_sda_T (iic_mux_sda_t_s),
|
|
|
|
|
.ps_intr_10 (ps_intrs[10]),
|
|
|
|
|
.ps_intr_11 (ps_intrs[11]),
|
|
|
|
|
.ps_intr_12 (ps_intrs[12]),
|
|
|
|
|
.ps_intr_13 (ps_intrs[13]),
|
|
|
|
|
.ps_intr_0 (ps_intrs[0]),
|
|
|
|
|
.ps_intr_1 (ps_intrs[1]),
|
|
|
|
|
.ps_intr_2 (ps_intrs[2]),
|
|
|
|
|
.ps_intr_3 (ps_intrs[3]),
|
|
|
|
|
.ps_intr_4 (ps_intrs[4]),
|
|
|
|
|
.ps_intr_5 (ps_intrs[5]),
|
|
|
|
|
.ps_intr_6 (ps_intrs[6]),
|
|
|
|
|
.ps_intr_7 (ps_intrs[7]),
|
|
|
|
|
.ps_intr_8 (ps_intrs[8]),
|
|
|
|
|
.ps_intr_9 (ps_intrs[9]),
|
|
|
|
|
.iic_fmc_intr(ps_intrs[13]),
|
|
|
|
|
.iic_ee2_intr(ps_intrs[12]),
|
|
|
|
|
.motcon2_s_d1_intr(ps_intrs[11]),
|
|
|
|
|
.motcon2_c_m1_intr(ps_intrs[10]),
|
|
|
|
|
.motcon2_ctrl_m1_intr(ps_intrs[9]),
|
|
|
|
|
.motcon2_s_d2_intr(ps_intrs[8]),
|
|
|
|
|
.motcon2_c_m2_intr(ps_intrs[7]),
|
|
|
|
|
.motcon2_ctrl_m2_intr(ps_intrs[6]),
|
|
|
|
|
.iic_ee2_scl_io(iic_ee2_scl_io),
|
|
|
|
|
.iic_ee2_sda_io(iic_ee2_sda_io),
|
|
|
|
|
.spi_csn_i (1'b1),
|
|
|
|
|
.spi_csn_o (fmc_spi1_sel1_rdc),
|
|
|
|
|
.spi_miso_i (fmc_spi1_miso),
|
|
|
|
|
.spi_mosi_i (1'b0),
|
|
|
|
|
.spi_mosi_o (fmc_spi1_mosi),
|
|
|
|
|
.spi_sclk_i (1'b0),
|
|
|
|
|
.spi_sclk_o (fmc_spi1_sck),
|
|
|
|
|
.refclk(refclk),
|
|
|
|
|
.refclk_rst(refclk_rst),
|
|
|
|
|
.otg_vbusoc (otg_vbusoc),
|
|
|
|
|
.spdif (spdif));
|
|
|
|
|
|
|
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
// ***************************************************************************
|
|
|
|
|
// ***************************************************************************
|
