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# device settings
set_global_assignment - name FAMILY " C y c l o n e V "
set_global_assignment - name DEVICE 5 CSXFC6D6F31C8ES
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# clocks
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set_location_assignment PIN_AF14 - to sys_clk
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set_instance_assignment - name IO_STANDARD " 1 . 5 V " - to sys_clk
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# vga
set_location_assignment PIN_W20 - to vga_clk
set_location_assignment PIN_AH3 - to vga_blank_n
set_location_assignment PIN_AG2 - to vga_sync_n
set_location_assignment PIN_AD12 - to vga_hs
set_location_assignment PIN_AC12 - to vga_vs
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set_location_assignment PIN_AF29 - to vga_b[ 7 ]
set_location_assignment PIN_AE28 - to vga_b[ 0 ]
set_location_assignment PIN_Y23 - to vga_b[ 1 ]
set_location_assignment PIN_Y24 - to vga_b[ 2 ]
set_location_assignment PIN_AG28 - to vga_b[ 3 ]
set_location_assignment PIN_AF28 - to vga_b[ 4 ]
set_location_assignment PIN_V23 - to vga_b[ 5 ]
set_location_assignment PIN_W24 - to vga_b[ 6 ]
set_location_assignment PIN_Y21 - to vga_g[ 0 ]
set_location_assignment PIN_AA25 - to vga_g[ 1 ]
set_location_assignment PIN_AB26 - to vga_g[ 2 ]
set_location_assignment PIN_AB22 - to vga_g[ 3 ]
set_location_assignment PIN_AB23 - to vga_g[ 4 ]
set_location_assignment PIN_AA24 - to vga_g[ 5 ]
set_location_assignment PIN_AB25 - to vga_g[ 6 ]
set_location_assignment PIN_AE27 - to vga_g[ 7 ]
set_location_assignment PIN_AG5 - to vga_r[ 0 ]
set_location_assignment PIN_AA12 - to vga_r[ 1 ]
set_location_assignment PIN_AB12 - to vga_r[ 2 ]
set_location_assignment PIN_AF6 - to vga_r[ 3 ]
set_location_assignment PIN_AG6 - to vga_r[ 4 ]
set_location_assignment PIN_AJ2 - to vga_r[ 5 ]
set_location_assignment PIN_AH5 - to vga_r[ 6 ]
set_location_assignment PIN_AJ1 - to vga_r[ 7 ]
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set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_blank_n
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_sync_n
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_hs
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_vs
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set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_g[ 7 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_g[ 0 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_g[ 1 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_g[ 2 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_g[ 3 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_g[ 4 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_g[ 5 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_g[ 6 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_r[ 0 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_r[ 1 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_r[ 2 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_r[ 3 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_r[ 4 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_r[ 5 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_r[ 6 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_r[ 7 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_b[ 0 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_b[ 1 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_b[ 2 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_b[ 3 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_b[ 4 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_b[ 5 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_b[ 6 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to vga_b[ 7 ]
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# led & switches
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set_location_assignment PIN_AD7 - to led[ 3 ]
set_location_assignment PIN_AE11 - to led[ 2 ]
set_location_assignment PIN_AD10 - to led[ 1 ]
set_location_assignment PIN_AF10 - to led[ 0 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to led[ 3 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to led[ 2 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to led[ 1 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to led[ 0 ]
set_location_assignment PIN_AD11 - to push_buttons[ 3 ]
set_location_assignment PIN_AD9 - to push_buttons[ 2 ]
set_location_assignment PIN_AE12 - to push_buttons[ 1 ]
set_location_assignment PIN_AE9 - to push_buttons[ 0 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to push_buttons[ 3 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to push_buttons[ 2 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to push_buttons[ 1 ]
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to push_buttons[ 0 ]
set_location_assignment PIN_AC29 - to dip_switches[ 3 ]
set_location_assignment PIN_AC28 - to dip_switches[ 2 ]
set_location_assignment PIN_V25 - to dip_switches[ 1 ]
set_location_assignment PIN_W25 - to dip_switches[ 0 ]
set_instance_assignment - name IO_STANDARD " 2 . 5 V " - to dip_switches[ 3 ]
set_instance_assignment - name IO_STANDARD " 2 . 5 V " - to dip_switches[ 2 ]
set_instance_assignment - name IO_STANDARD " 2 . 5 V " - to dip_switches[ 1 ]
set_instance_assignment - name IO_STANDARD " 2 . 5 V " - to dip_switches[ 0 ]
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# uart
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set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to uart0_tx
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to uart0_rx
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# spim1 (lcd)
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set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to spim1_ss0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to spim1_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to spim1_mosi
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to spim1_miso
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# usb
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_stp
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_dir
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_nxt
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d1
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d2
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d3
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d4
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d5
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d6
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to usb1_d7
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# sdio
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set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to sdio_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to sdio_cmd
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to sdio_d0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to sdio_d1
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to sdio_d2
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to sdio_d3
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# qspi
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to qspi_ss0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to qspi_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to qspi_io0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to qspi_io1
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to qspi_io2
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V C M O S " - to qspi_io3
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# ethernet
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_tx_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_tx_ctl
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_txd0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_txd1
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_txd2
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_txd3
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rx_clk
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rx_ctl
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rxd0
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rxd1
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rxd2
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_rxd3
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_mdc
set_instance_assignment - name IO_STANDARD " 3 . 3 - V L V T T L " - to eth1_mdio
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# ddr
set_instance_assignment - name D5_DELAY 2 - to ddr3_ck_p
set_instance_assignment - name D5_DELAY 2 - to ddr3_ck_n
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 0 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 1 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 2 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 3 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 4 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 5 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 6 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 7 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 8 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 9 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 10 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 11 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 12 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 13 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_a[ 14 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_ba[ 0 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_ba[ 1 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_ba[ 2 ]
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_cas_n
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_cke
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_cs_n
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_odt
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_ras_n
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_reset_n
set_instance_assignment - name CURRENT_STRENGTH_NEW " M A X I M U M C U R R E N T " - to ddr3_we_n
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uio_pads| dq_ddio[ 0 ] .read_capture_clk_buffer
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uio_pads| dq_ddio[ 1 ] .read_capture_clk_buffer
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uio_pads| dq_ddio[ 2 ] .read_capture_clk_buffer
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uio_pads| dq_ddio[ 3 ] .read_capture_clk_buffer
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_wraddress[ 0 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_wraddress[ 1 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_wraddress[ 2 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_wraddress[ 3 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_write_side[ 0 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_write_side[ 1 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_write_side[ 2 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| uread_datapath| reset_n_fifo_write_side[ 3 ]
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| ureset| phy_reset_mem_stable_n
set_instance_assignment - name GLOBAL_SIGNAL OFF - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| p0| umemphy| ureset| phy_reset_n
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 0 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 1 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 2 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 3 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 4 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 5 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 6 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 7 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 8 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 9 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 10 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 11 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 12 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 13 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 14 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 15 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 16 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 17 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 18 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 19 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 20 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 21 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 22 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 23 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 24 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 25 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 26 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 27 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 28 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 29 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 30 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 31 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 0 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 1 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 2 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 3 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 0 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 1 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 2 ]
set_instance_assignment - name INPUT_TERMINATION " P A R A L L E L 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 3 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_ck_p
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_ck_n
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_p[ 0 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_p[ 1 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_p[ 2 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_p[ 3 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_n[ 0 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_n[ 1 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_n[ 2 ]
set_instance_assignment - name IO_STANDARD " D I F F E R E N T I A L 1 . 5 - V S S T L C L A S S I " - to ddr3_dqs_n[ 3 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 0 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 1 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 2 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 3 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 4 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 5 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 6 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 7 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 8 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 9 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 10 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 11 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 12 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 13 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_a[ 14 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_ba[ 0 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_ba[ 1 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_ba[ 2 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_cas_n
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_cke
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_cs_n
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dm[ 0 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dm[ 1 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dm[ 2 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dm[ 3 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 0 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 1 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 2 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 3 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 4 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 5 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 6 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 7 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 8 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 9 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 10 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 11 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 12 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 13 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 14 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 15 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 16 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 17 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 18 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 19 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 20 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 21 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 22 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 23 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 24 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 25 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 26 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 27 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 28 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 29 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 30 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_dq[ 31 ]
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_odt
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_ras_n
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_reset_n
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_we_n
set_instance_assignment - name IO_STANDARD " S S T L - 1 5 C L A S S I " - to ddr3_oct_rzqin
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dm[ 0 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dm[ 1 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dm[ 2 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dm[ 3 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 0 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 1 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 2 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 3 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 4 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 5 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 6 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 7 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 8 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 9 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 10 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 11 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 12 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 13 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 14 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 15 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 16 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 17 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 18 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 19 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 20 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 21 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 22 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 23 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 24 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 25 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 26 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 27 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 28 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 29 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 30 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dq[ 31 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 0 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 1 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 2 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_p[ 3 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 0 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 1 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 2 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H C A L I B R A T I O N " - to ddr3_dqs_n[ 3 ]
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H O U T C A L I B R A T I O N " - to ddr3_ck_p
set_instance_assignment - name OUTPUT_TERMINATION " S E R I E S 5 0 O H M W I T H O U T C A L I B R A T I O N " - to ddr3_ck_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 3 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 4 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 5 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 6 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 7 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 8 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 9 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 10 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 11 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 12 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 13 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_a[ 14 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ba[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ba[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ba[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_cas_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ck_p
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ck_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_cke
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_cs_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dm[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dm[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dm[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dm[ 3 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 3 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 4 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 5 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 6 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 7 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 8 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 9 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 10 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 11 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 12 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 13 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 14 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 15 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 16 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 17 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 18 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 19 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 20 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 21 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 22 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 23 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 24 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 25 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 26 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 27 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 28 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 29 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 30 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dq[ 31 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_p[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_p[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_p[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_p[ 3 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_n[ 0 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_n[ 1 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_n[ 2 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_dqs_n[ 3 ]
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_odt
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_ras_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_reset_n
set_instance_assignment - name PACKAGE_SKEW_COMPENSATION OFF - to ddr3_we_n
set_instance_assignment - name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst
set_instance_assignment - name PLL_COMPENSATION_MODE DIRECT - to i_system_bd| sys_hps| hps_io| border| hps_sdram_inst| pll0| fbout
# globals
set_global_assignment - name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
set_global_assignment - name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
set_global_assignment - name OPTIMIZE_MULTI_CORNER_TIMING ON
2014-07-02 18:56:00 +00:00
set_global_assignment - name OPTIMIZE_HOLD_TIMING " A L L P A T H S "
2014-07-01 17:05:26 +00:00
set_global_assignment - name ECO_REGENERATE_REPORT ON
set_global_assignment - name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment - name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment - name USE_TIMEQUEST_TIMING_ANALYZER ON
2014-07-02 18:56:00 +00:00
set_global_assignment - name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment - name STRATIX_DEVICE_IO_STANDARD " 2 . 5 V "
2014-07-01 17:05:26 +00:00
set_global_assignment - name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment - name TIMEQUEST_DO_CCPP_REMOVAL ON
2015-06-04 15:00:25 +00:00
set_global_assignment - name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir / projects/ scripts/ adi_tquest.tcl
2014-07-01 17:05:26 +00:00
set_global_assignment - name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
2014-07-02 18:56:00 +00:00
