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pluto_hdl_adi/library/axi_pwm_gen/Makefile

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axi_pwm_gen: Initial commit axi_pwm_gen is based on util_pulse_gen, it introduces the option of phase option between pulses(PWMs) and external synchronization. Documentation available at https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-03-26 08:07:54 +00:00
####################################################################################
library & projects: Update Makefiles Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-18 13:15:22 +00:00
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
Makefiles: Update header with the appropriate license
2021-09-15 15:03:11 +00:00
### SPDX short identifier: BSD-1-Clause
axi_pwm_gen: Initial commit axi_pwm_gen is based on util_pulse_gen, it introduces the option of phase option between pulses(PWMs) and external synchronization. Documentation available at https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-03-26 08:07:54 +00:00
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_pwm_gen
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += axi_pwm_gen.v
GENERIC_DEPS += axi_pwm_gen_1.v
GENERIC_DEPS += axi_pwm_gen_regmap.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += axi_pwm_gen_constr.ttcl
XILINX_DEPS += axi_pwm_gen_ip.tcl
XILINX_LIB_DEPS += util_cdc
axi_pwm_gen: add: intel support (#1080) Signed-off-by: Jem Geronimo <johnerasmusmari.geronimo@analog.com>
2023-02-07 10:27:04 +00:00
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
axi_pwm_gen: Update timing constraints, hw.tcl and sdc files. Not using util_cdc_constr.tcl
2023-02-20 10:27:57 +00:00
INTEL_DEPS += ../util_cdc/sync_bits.v
INTEL_DEPS += ../util_cdc/sync_data.v
INTEL_DEPS += axi_pwm_gen_constr.sdc
axi_pwm_gen: add: intel support (#1080) Signed-off-by: Jem Geronimo <johnerasmusmari.geronimo@analog.com>
2023-02-07 10:27:04 +00:00
INTEL_DEPS += axi_pwm_gen_hw.tcl
axi_pwm_gen: Initial commit axi_pwm_gen is based on util_pulse_gen, it introduces the option of phase option between pulses(PWMs) and external synchronization. Documentation available at https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-03-26 08:07:54 +00:00
include ../scripts/library.mk