266 lines
9.9 KiB
VHDL
266 lines
9.9 KiB
VHDL
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---- ----
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---- WISHBONE SPDIF IP Core ----
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---- ----
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---- This file is part of the SPDIF project ----
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---- http://www.opencores.org/cores/spdif_interface/ ----
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---- ----
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---- Description ----
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---- Sample decoder. Extract sample words and write to sample ----
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---- buffer. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.4 2004/07/11 16:19:50 gedra
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-- Bug-fix.
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--
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-- Revision 1.3 2004/06/26 14:14:47 gedra
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-- Converted to numeric_std and fixed a few bugs.
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--
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-- Revision 1.2 2004/06/16 19:04:09 gedra
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-- Fixed a few bugs.
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--
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-- Revision 1.1 2004/06/13 18:07:47 gedra
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-- Frame decoder and sample extractor
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--
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity rx_decode is
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generic (DATA_WIDTH: integer range 16 to 32;
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ADDR_WIDTH: integer range 8 to 64);
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port (
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up_clk: in std_logic;
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conf_rxen: in std_logic;
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conf_sample: in std_logic;
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conf_valid: in std_logic;
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conf_mode: in std_logic_vector(3 downto 0);
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conf_blken: in std_logic;
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conf_valen: in std_logic;
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conf_useren: in std_logic;
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conf_staten: in std_logic;
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conf_paren: in std_logic;
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lock: in std_logic;
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rx_data: in std_logic;
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rx_data_en: in std_logic;
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rx_block_start: in std_logic;
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rx_frame_start: in std_logic;
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rx_channel_a: in std_logic;
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wr_en: out std_logic;
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wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
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wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
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stat_paritya: out std_logic;
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stat_parityb: out std_logic;
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stat_lsbf: out std_logic;
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stat_hsbf: out std_logic);
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end rx_decode;
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architecture rtl of rx_decode is
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signal adr_cnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
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type samp_states is (IDLE, CHA_SYNC, GET_SAMP, PAR_CHK);
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signal sampst : samp_states;
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signal bit_cnt, par_cnt : integer range 0 to 31;
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signal samp_start : integer range 0 to 15;
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signal tmp_data : std_logic_vector(31 downto 0);
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signal tmp_stat : std_logic_vector(4 downto 0);
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signal valid, next_is_a, blk_start : std_logic;
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begin
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-- output data
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OD32: if DATA_WIDTH = 32 generate
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--wr_data(31 downto 27) <= tmp_stat;
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wr_data(31 downto 0) <= tmp_data(31 downto 0);
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end generate OD32;
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OD16: if DATA_WIDTH = 16 generate
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wr_data(15 downto 0) <= tmp_data(15 downto 0);
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end generate OD16;
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-- State machine extracting audio samples
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SAEX: process (up_clk, conf_rxen)
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begin -- process SAEX
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if conf_rxen = '0' then
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adr_cnt <= 0;
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next_is_a <= '1';
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wr_en <= '0';
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wr_addr <= (others => '0');
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tmp_data <= (others => '0');
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par_cnt <= 0;
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blk_start <= '0';
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stat_paritya <= '0';
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stat_parityb <= '0';
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stat_lsbf <= '0';
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stat_hsbf <= '0';
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valid <= '0';
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bit_cnt <= 0;
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sampst <= IDLE;
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tmp_stat <= (others => '0');
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elsif rising_edge(up_clk) then
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--extract and store samples
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case sampst is
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when IDLE =>
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next_is_a <= '1';
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if lock = '1' and conf_sample = '1' then
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sampst <= CHA_SYNC;
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end if;
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when CHA_SYNC =>
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wr_addr <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1));
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wr_en <= '0';
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bit_cnt <= 0;
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valid <= '0';
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par_cnt <= 0;
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stat_paritya <= '0';
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stat_parityb <= '0';
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stat_lsbf <= '0';
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stat_hsbf <= '0';
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--tmp_data(31 downto 0) <= (others => '0');
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if rx_block_start = '1' and conf_blken = '1' then
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blk_start <= '1';
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end if;
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if rx_frame_start = '1' then --and rx_channel_a = '1' then --next_is_a then
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next_is_a <= rx_channel_a;
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if(rx_channel_a = '1') then
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tmp_data(31 downto 0) <= (others => '0');
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end if;
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sampst <= GET_SAMP;
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end if;
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when GET_SAMP =>
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tmp_stat(0) <= blk_start;
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if rx_data_en = '1' then
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bit_cnt <= bit_cnt + 1;
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-- audio part
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if bit_cnt >= samp_start and bit_cnt <= 23 then
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if(next_is_a = '1') then
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tmp_data(bit_cnt - samp_start) <= rx_data;
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else
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tmp_data(bit_cnt + 16 - samp_start) <= rx_data;
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end if;
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end if;
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-- status bits
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case bit_cnt is
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when 24 => -- validity bit
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valid <= rx_data;
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if conf_valen = '1' then
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tmp_stat(1) <= rx_data;
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else
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tmp_stat(1) <= '0';
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end if;
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when 25 => -- user data
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if conf_useren = '1' then
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tmp_stat(2) <= rx_data;
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else
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tmp_stat(2) <= '0';
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end if;
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when 26 => -- channel status
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if conf_staten = '1' then
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tmp_stat(3) <= rx_data;
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else
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tmp_stat(3) <= '0';
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end if;
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when 27 => -- parity bit
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if conf_paren = '1' then
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tmp_stat(4) <= rx_data;
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else
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tmp_stat(4) <= '0';
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end if;
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when others =>
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null;
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end case;
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-- parity: count number of 1's
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if rx_data = '1' then
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par_cnt <= par_cnt + 1;
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end if;
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end if;
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if bit_cnt = 28 then
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sampst <= PAR_CHK;
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end if;
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when PAR_CHK =>
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blk_start <= '0';
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if (((valid = '0' and conf_valid = '1') or conf_valid = '0') and (next_is_a = '0')) then
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wr_en <= '1';
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end if;
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-- parity check
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if par_cnt mod 2 /= 0 then
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if rx_channel_a = '1' then
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stat_paritya <= '1';
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else
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stat_parityb <= '1';
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end if;
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end if;
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-- address counter
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if adr_cnt < 2**(ADDR_WIDTH - 1) - 1 then
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adr_cnt <= adr_cnt + 1;
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else
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adr_cnt <= 0;
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stat_hsbf <= '1'; -- signal high buffer full
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end if;
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if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then
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stat_lsbf <= '1'; -- signal low buffer full
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end if;
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sampst <= CHA_SYNC;
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when others =>
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sampst <= IDLE;
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end case;
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end if;
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end process SAEX;
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-- determine sample resolution from mode bits in 32bit mode
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M32: if DATA_WIDTH = 32 generate
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samp_start <= 8 when conf_mode = "0000" else
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7 when conf_mode = "0001" else
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6 when conf_mode = "0010" else
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5 when conf_mode = "0011" else
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4 when conf_mode = "0100" else
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3 when conf_mode = "0101" else
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2 when conf_mode = "0110" else
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1 when conf_mode = "0111" else
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0 when conf_mode = "1000" else
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8;
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end generate M32;
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-- in 16bit mode only 16bit of audio is supported
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M16: if DATA_WIDTH = 16 generate
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samp_start <= 8;
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end generate M16;
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end rtl;
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