pluto_hdl_adi/projects/fmcadc2/vc707/system_bd.tcl

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## FIFO depth is 16Mb - 1M samples
set adc_fifo_address_width 18
## NOTE: With this configuration the #36Kb BRAM utilization is at ~68%
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source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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source ../common/fmcadc2_bd.tcl