2019-01-22 13:19:47 +00:00
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set dac_fifo_name avl_ad9152_fifo
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set dac_data_width 128
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set dac_dma_data_width 128
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2016-07-08 09:00:37 +00:00
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2016-10-10 10:36:48 +00:00
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# ad9152-xcvr
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2017-10-25 13:41:26 +00:00
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add_instance ad9152_jesd204 adi_jesd204
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set_instance_parameter_value ad9152_jesd204 {ID} {0}
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set_instance_parameter_value ad9152_jesd204 {TX_OR_RX_N} {1}
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set_instance_parameter_value ad9152_jesd204 {LANE_RATE} {12333.3}
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set_instance_parameter_value ad9152_jesd204 {REFCLK_FREQUENCY} {616.665}
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set_instance_parameter_value ad9152_jesd204 {NUM_OF_LANES} {4}
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set_instance_parameter_value ad9152_jesd204 {LANE_MAP} {0 3 1 2}
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add_connection sys_clk.clk ad9152_jesd204.sys_clk
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add_connection sys_clk.clk_reset ad9152_jesd204.sys_resetn
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2016-07-08 09:00:37 +00:00
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add_interface tx_ref_clk clock sink
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2017-10-25 13:41:26 +00:00
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set_interface_property tx_ref_clk EXPORT_OF ad9152_jesd204.ref_clk
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add_interface tx_serial_data conduit end
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set_interface_property tx_serial_data EXPORT_OF ad9152_jesd204.serial_data
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2016-07-08 09:00:37 +00:00
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add_interface tx_sysref conduit end
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2017-10-25 13:41:26 +00:00
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set_interface_property tx_sysref EXPORT_OF ad9152_jesd204.sysref
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2016-07-08 09:00:37 +00:00
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add_interface tx_sync conduit end
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2017-10-25 13:41:26 +00:00
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set_interface_property tx_sync EXPORT_OF ad9152_jesd204.sync
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2016-10-10 10:36:48 +00:00
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# ad9152-core
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2016-07-08 09:00:37 +00:00
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2017-05-12 17:40:14 +00:00
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add_instance axi_ad9152_core axi_ad9152
|
2016-07-08 09:00:37 +00:00
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2017-10-25 13:41:26 +00:00
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add_connection ad9152_jesd204.link_clk axi_ad9152_core.if_tx_clk
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add_connection axi_ad9152_core.if_tx_data ad9152_jesd204.link_data
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2016-07-08 09:00:37 +00:00
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add_connection sys_clk.clk_reset axi_ad9152_core.s_axi_reset
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add_connection sys_clk.clk axi_ad9152_core.s_axi_clock
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# ad9152-unpack
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|
2018-10-04 10:41:11 +00:00
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add_instance util_ad9152_upack util_upack2
|
2016-07-08 09:00:37 +00:00
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set_instance_parameter_value util_ad9152_upack {NUM_OF_CHANNELS} {2}
|
2018-10-04 10:41:11 +00:00
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set_instance_parameter_value util_ad9152_upack {SAMPLES_PER_CHANNEL} {4}
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set_instance_parameter_value util_ad9152_upack {SAMPLE_DATA_WIDTH} {16}
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set_instance_parameter_value util_ad9152_upack {INTERFACE_TYPE} {1}
|
2016-07-08 09:00:37 +00:00
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|
2018-10-04 10:41:11 +00:00
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add_connection ad9152_jesd204.link_clk util_ad9152_upack.clk
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add_connection ad9152_jesd204.link_reset util_ad9152_upack.reset
|
2016-07-08 09:00:37 +00:00
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add_connection axi_ad9152_core.dac_ch_0 util_ad9152_upack.dac_ch_0
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add_connection axi_ad9152_core.dac_ch_1 util_ad9152_upack.dac_ch_1
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|
2017-10-25 13:41:26 +00:00
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# dac fifo
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|
2019-01-22 13:19:47 +00:00
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|
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
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|
2017-10-25 13:41:26 +00:00
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|
add_interface tx_fifo_bypass conduit end
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|
set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9152_fifo.if_bypass
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|
add_connection ad9152_jesd204.link_clk avl_ad9152_fifo.if_dac_clk
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|
add_connection ad9152_jesd204.link_reset avl_ad9152_fifo.if_dac_rst
|
2018-10-04 10:41:11 +00:00
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|
add_connection util_ad9152_upack.if_packed_fifo_rd_en avl_ad9152_fifo.if_dac_valid
|
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|
add_connection avl_ad9152_fifo.if_dac_data util_ad9152_upack.if_packed_fifo_rd_data
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|
add_connection avl_ad9152_fifo.if_dac_dunf axi_ad9152_core.if_dac_dunf
|
2017-10-25 13:41:26 +00:00
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|
2016-07-08 09:00:37 +00:00
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|
|
# ad9152-dma
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|
2017-05-12 17:40:14 +00:00
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|
|
add_instance axi_ad9152_dma axi_dmac
|
2016-07-08 09:00:37 +00:00
|
|
|
set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_SRC} {128}
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|
|
|
|
set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_DEST} {128}
|
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|
|
|
set_instance_parameter_value axi_ad9152_dma {DMA_2D_TRANSFER} {0}
|
2017-10-25 13:41:26 +00:00
|
|
|
set_instance_parameter_value axi_ad9152_dma {SYNC_TRANSFER_START} {0}
|
|
|
|
|
set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_DEST} {1}
|
2016-07-08 09:00:37 +00:00
|
|
|
set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_SRC} {0}
|
2017-10-25 13:41:26 +00:00
|
|
|
set_instance_parameter_value axi_ad9152_dma {FIFO_SIZE} {16}
|
2019-05-16 07:14:25 +00:00
|
|
|
set_instance_parameter_value axi_ad9152_dma {HAS_AXIS_TLAST} {1}
|
2017-10-25 13:41:26 +00:00
|
|
|
|
|
|
|
|
add_connection sys_clk.clk avl_ad9152_fifo.if_dma_clk
|
|
|
|
|
add_connection sys_clk.clk_reset avl_ad9152_fifo.if_dma_rst
|
|
|
|
|
add_connection sys_clk.clk axi_ad9152_dma.if_m_axis_aclk
|
2019-05-16 07:14:25 +00:00
|
|
|
add_connection axi_ad9152_dma.m_axis avl_ad9152_fifo.s_axis
|
2017-10-25 13:41:26 +00:00
|
|
|
add_connection axi_ad9152_dma.if_m_axis_xfer_req avl_ad9152_fifo.if_dma_xfer_req
|
2016-07-08 09:00:37 +00:00
|
|
|
add_connection sys_clk.clk_reset axi_ad9152_dma.s_axi_reset
|
|
|
|
|
add_connection sys_clk.clk axi_ad9152_dma.s_axi_clock
|
2017-10-25 13:41:26 +00:00
|
|
|
add_connection sys_clk.clk_reset axi_ad9152_dma.m_src_axi_reset
|
|
|
|
|
add_connection sys_clk.clk axi_ad9152_dma.m_src_axi_clock
|
2016-07-08 09:00:37 +00:00
|
|
|
|
2016-10-10 10:36:48 +00:00
|
|
|
# ad9680-xcvr
|
|
|
|
|
|
2017-10-25 13:41:26 +00:00
|
|
|
add_instance ad9680_jesd204 adi_jesd204
|
|
|
|
|
set_instance_parameter_value ad9680_jesd204 {ID} {1}
|
|
|
|
|
set_instance_parameter_value ad9680_jesd204 {TX_OR_RX_N} {0}
|
|
|
|
|
set_instance_parameter_value ad9680_jesd204 {LANE_RATE} {12333.3}
|
|
|
|
|
set_instance_parameter_value ad9680_jesd204 {REFCLK_FREQUENCY} {616.665}
|
|
|
|
|
set_instance_parameter_value ad9680_jesd204 {NUM_OF_LANES} {4}
|
2020-08-25 06:20:00 +00:00
|
|
|
set_instance_parameter_value ad9680_jesd204 {INPUT_PIPELINE_STAGES} {1}
|
2017-10-25 13:41:26 +00:00
|
|
|
|
|
|
|
|
add_connection sys_clk.clk ad9680_jesd204.sys_clk
|
|
|
|
|
add_connection sys_clk.clk_reset ad9680_jesd204.sys_resetn
|
2016-10-10 10:36:48 +00:00
|
|
|
add_interface rx_ref_clk clock sink
|
2017-10-25 13:41:26 +00:00
|
|
|
set_interface_property rx_ref_clk EXPORT_OF ad9680_jesd204.ref_clk
|
|
|
|
|
add_interface rx_serial_data conduit end
|
|
|
|
|
set_interface_property rx_serial_data EXPORT_OF ad9680_jesd204.serial_data
|
2016-10-10 10:36:48 +00:00
|
|
|
add_interface rx_sysref conduit end
|
2017-10-25 13:41:26 +00:00
|
|
|
set_interface_property rx_sysref EXPORT_OF ad9680_jesd204.sysref
|
2016-10-10 10:36:48 +00:00
|
|
|
add_interface rx_sync conduit end
|
2017-10-25 13:41:26 +00:00
|
|
|
set_interface_property rx_sync EXPORT_OF ad9680_jesd204.sync
|
2016-10-10 10:36:48 +00:00
|
|
|
|
2016-07-08 09:00:37 +00:00
|
|
|
# ad9680
|
|
|
|
|
|
2017-05-12 17:40:14 +00:00
|
|
|
add_instance axi_ad9680_core axi_ad9680
|
2016-07-08 09:00:37 +00:00
|
|
|
|
2017-10-25 13:41:26 +00:00
|
|
|
add_connection ad9680_jesd204.link_clk axi_ad9680_core.if_rx_clk
|
|
|
|
|
add_connection ad9680_jesd204.link_sof axi_ad9680_core.if_rx_sof
|
|
|
|
|
add_connection ad9680_jesd204.link_data axi_ad9680_core.if_rx_data
|
2016-07-08 09:00:37 +00:00
|
|
|
add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
|
|
|
|
|
add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
|
|
|
|
|
|
|
|
|
|
# ad9680-pack
|
|
|
|
|
|
2018-10-04 10:41:11 +00:00
|
|
|
add_instance util_ad9680_cpack util_cpack2
|
2016-07-08 09:00:37 +00:00
|
|
|
set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
|
2018-10-04 10:41:11 +00:00
|
|
|
set_instance_parameter_value util_ad9680_cpack {SAMPLES_PER_CHANNEL} {4}
|
|
|
|
|
set_instance_parameter_value util_ad9680_cpack {SAMPLE_DATA_WIDTH} {16}
|
2016-07-08 09:00:37 +00:00
|
|
|
|
2018-10-04 10:41:11 +00:00
|
|
|
add_connection ad9680_jesd204.link_clk util_ad9680_cpack.clk
|
|
|
|
|
add_connection ad9680_jesd204.link_reset util_ad9680_cpack.reset
|
2016-07-08 09:00:37 +00:00
|
|
|
add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
|
|
|
|
|
add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
|
|
|
|
|
|
|
|
|
|
# ad9680-fifo
|
|
|
|
|
|
2017-05-12 17:40:14 +00:00
|
|
|
add_instance ad9680_adcfifo util_adcfifo
|
2016-07-08 09:00:37 +00:00
|
|
|
set_instance_parameter_value ad9680_adcfifo {ADC_DATA_WIDTH} {128}
|
|
|
|
|
set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} {128}
|
|
|
|
|
set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
|
|
|
|
|
|
|
|
|
|
add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
|
2017-10-25 13:41:26 +00:00
|
|
|
add_connection ad9680_jesd204.link_clk ad9680_adcfifo.if_adc_clk
|
2018-10-04 10:41:11 +00:00
|
|
|
add_connection util_ad9680_cpack.if_packed_fifo_wr_en ad9680_adcfifo.if_adc_wr
|
|
|
|
|
add_connection util_ad9680_cpack.if_packed_fifo_wr_data ad9680_adcfifo.if_adc_wdata
|
2017-10-25 13:41:26 +00:00
|
|
|
add_connection sys_clk.clk ad9680_adcfifo.if_dma_clk
|
2016-07-08 09:00:37 +00:00
|
|
|
|
|
|
|
|
# ad9680-dma
|
|
|
|
|
|
2017-05-12 17:40:14 +00:00
|
|
|
add_instance axi_ad9680_dma axi_dmac
|
2016-07-08 09:00:37 +00:00
|
|
|
set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_SRC} {128}
|
|
|
|
|
set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_DEST} {128}
|
|
|
|
|
set_instance_parameter_value axi_ad9680_dma {DMA_LENGTH_WIDTH} {24}
|
|
|
|
|
set_instance_parameter_value axi_ad9680_dma {DMA_2D_TRANSFER} {0}
|
2017-11-01 07:31:19 +00:00
|
|
|
set_instance_parameter_value axi_ad9680_dma {SYNC_TRANSFER_START} {0}
|
2016-07-08 09:00:37 +00:00
|
|
|
set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0}
|
|
|
|
|
set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0}
|
|
|
|
|
set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1}
|
|
|
|
|
|
2017-10-25 13:41:26 +00:00
|
|
|
add_connection sys_clk.clk axi_ad9680_dma.if_s_axis_aclk
|
2019-05-16 07:14:25 +00:00
|
|
|
add_connection ad9680_adcfifo.m_axis axi_ad9680_dma.s_axis
|
2016-07-08 09:00:37 +00:00
|
|
|
add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req
|
|
|
|
|
add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf
|
|
|
|
|
add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset
|
|
|
|
|
add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock
|
2017-10-25 13:41:26 +00:00
|
|
|
add_connection sys_clk.clk_reset axi_ad9680_dma.m_dest_axi_reset
|
|
|
|
|
add_connection sys_clk.clk axi_ad9680_dma.m_dest_axi_clock
|
2016-07-08 09:00:37 +00:00
|
|
|
|
2016-10-10 10:36:48 +00:00
|
|
|
# reconfig sharing
|
|
|
|
|
|
2017-10-25 13:41:26 +00:00
|
|
|
for {set i 0} {$i < 4} {incr i} {
|
|
|
|
|
add_instance avl_adxcfg_${i} avl_adxcfg
|
|
|
|
|
add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk
|
|
|
|
|
add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n
|
|
|
|
|
add_connection avl_adxcfg_${i}.rcfg_m0 ad9152_jesd204.phy_reconfig_${i}
|
|
|
|
|
add_connection avl_adxcfg_${i}.rcfg_m1 ad9680_jesd204.phy_reconfig_${i}
|
|
|
|
|
}
|
2016-10-10 10:36:48 +00:00
|
|
|
|
2016-07-08 09:00:37 +00:00
|
|
|
# addresses
|
|
|
|
|
|
2017-10-25 13:41:26 +00:00
|
|
|
ad_cpu_interconnect 0x00400000 ad9152_jesd204.link_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00424000 ad9152_jesd204.link_management
|
|
|
|
|
ad_cpu_interconnect 0x00425000 ad9152_jesd204.link_pll_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00426000 ad9152_jesd204.lane_pll_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00428000 avl_adxcfg_0.rcfg_s0
|
|
|
|
|
ad_cpu_interconnect 0x00429000 avl_adxcfg_1.rcfg_s0
|
|
|
|
|
ad_cpu_interconnect 0x0042a000 avl_adxcfg_2.rcfg_s0
|
|
|
|
|
ad_cpu_interconnect 0x0042b000 avl_adxcfg_3.rcfg_s0
|
|
|
|
|
ad_cpu_interconnect 0x0042c000 axi_ad9152_dma.s_axi
|
2018-11-20 14:00:55 +00:00
|
|
|
ad_cpu_interconnect 0x00434000 axi_ad9152_core.s_axi
|
2017-10-25 13:41:26 +00:00
|
|
|
|
|
|
|
|
ad_cpu_interconnect 0x00440000 ad9680_jesd204.link_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00444000 ad9680_jesd204.link_management
|
|
|
|
|
ad_cpu_interconnect 0x00445000 ad9680_jesd204.link_pll_reconfig
|
|
|
|
|
ad_cpu_interconnect 0x00448000 avl_adxcfg_0.rcfg_s1
|
|
|
|
|
ad_cpu_interconnect 0x00449000 avl_adxcfg_1.rcfg_s1
|
|
|
|
|
ad_cpu_interconnect 0x0044a000 avl_adxcfg_2.rcfg_s1
|
|
|
|
|
ad_cpu_interconnect 0x0044b000 avl_adxcfg_3.rcfg_s1
|
|
|
|
|
ad_cpu_interconnect 0x0044c000 axi_ad9680_dma.s_axi
|
|
|
|
|
ad_cpu_interconnect 0x00450000 axi_ad9680_core.s_axi
|
2017-06-16 13:02:26 +00:00
|
|
|
|
|
|
|
|
# dma interconnects
|
|
|
|
|
|
|
|
|
|
ad_dma_interconnect axi_ad9152_dma.m_src_axi
|
|
|
|
|
ad_dma_interconnect axi_ad9680_dma.m_dest_axi
|
2016-07-08 09:00:37 +00:00
|
|
|
|
|
|
|
|
# interrupts
|
|
|
|
|
|
2017-10-25 13:41:26 +00:00
|
|
|
ad_cpu_interrupt 8 ad9680_jesd204.interrupt
|
|
|
|
|
ad_cpu_interrupt 9 ad9152_jesd204.interrupt
|
2017-06-16 13:02:26 +00:00
|
|
|
ad_cpu_interrupt 10 axi_ad9680_dma.interrupt_sender
|
|
|
|
|
ad_cpu_interrupt 11 axi_ad9152_dma.interrupt_sender
|
