pluto_hdl_adi/library/util_clkdiv/util_clkdiv_alt.v

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// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
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// The user should read each of these license terms, and understand the
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`timescale 1ns/100ps

// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if
// clk_sel is 1. Provides a glitch free output clock
// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives

module util_clkdiv_alt #(
  parameter SIM_DEVICE = "CYCLONE5",
  parameter CLOCK_TYPE = "Global Clock") (

  input   clk,
  input   reset,
  output  clk_out,
  output  reset_out
 );

reg enable;
reg reset_d1;

assign reset_out = reset | reset_d1;

always @(posedge clk) begin
  reset_d1 <= reset;
end

always @(posedge clk) begin
  enable <= ~enable;
end
  
generate if (SIM_DEVICE == "CYCLONE5") begin
	cyclonev_clkena #(
		.clock_type ("Global Clock"),
		.ena_register_mode ("falling edge"),
		.lpm_type ("cyclonev_clkena")
  ) clock_divider_by_2 ( 
	.ena(enable),
	.enaout(),
	.inclk(clk),
//	.clkselect (2'b0),
	.outclk(clk_out));

end endgenerate

endmodule  // util_clkdiv_alt