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pluto_hdl_adi/projects/adrv9371x/zc706/system_bd.tcl

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Tcl
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adrv9371x- added
2016-05-20 15:46:25 +00:00
projects/system_bd- adc/dac fifo board designs
2017-02-27 21:05:21 +00:00
set dac_fifo_name axi_ad9371_dacfifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
adrv9371x- added
2016-05-20 15:46:25 +00:00
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
file renamed; sed output; fingers crossed
2017-02-22 20:56:37 +00:00
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
adrv9371x: Separate ps7 assignaments from common Move the assignaments/connections for ps7 from common/adrv9371_bd to zc706/system_bd
2017-08-18 13:21:34 +00:00
adrv9371: Increase FCLK2 to 200MHz to support max sampling rates This fixes an issue seen when using 307.2 MSPS on the Observation RX. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2018-01-09 14:20:06 +00:00
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 200
adrv9371x: Separate ps7 assignaments from common Move the assignaments/connections for ps7 from common/adrv9371_bd to zc706/system_bd
2017-08-18 13:21:34 +00:00
adrv9371x- added
2016-05-20 15:46:25 +00:00
source ../common/adrv9371x_bd.tcl
adrv9371x: Separate ps7 assignaments from common Move the assignaments/connections for ps7 from common/adrv9371_bd to zc706/system_bd
2017-08-18 13:21:34 +00:00
ad_connect sys_dma_clk sys_ps7/FCLK_CLK2
ad_connect sys_ps7/FCLK_RESET2_N sys_dma_rstgen/ext_reset_in