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pluto_hdl_adi/library/axi_adrv9001/axi_adrv9001_constr.sdc

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axi_adrv9001: Double sync control lines between interface 1 and 2
2021-02-17 10:02:39 +00:00
set script_dir [file dirname [info script]]
source "$script_dir/util_cdc_constr.tcl"
library:axi_adrv9001: Initial version ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.
2020-06-02 06:27:27 +00:00
set_false_path -from [get_registers *i_dev_if|up_enable_int*] -to [get_registers *i_dev_if|enable_up_m1*]
set_false_path -from [get_registers *i_dev_if|up_txnrx_int*] -to [get_registers *i_dev_if|txnrx_up_m1*]
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_state_m1*]
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle_m1*]
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_data*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_data_cntrl*]
axi_adrv9001: Double sync control lines between interface 1 and 2
2021-02-17 10:02:39 +00:00
util_cdc_sync_bits_constr {*|sync_bits:i_rx1_ctrl_sync}
util_cdc_sync_bits_constr {*|sync_bits:i_tx1_ctrl_sync}